Marco Ottavi
YOU?
Author Swipe
View article: Neutron Resilience of Flexible Perovskite Solar Cells Using PTAA‐Derived Hole Transport Layers
Neutron Resilience of Flexible Perovskite Solar Cells Using PTAA‐Derived Hole Transport Layers Open
Flexible perovskite solar cells hold promise of being an enabling technology for space missions: by reducing the encumbrance and weight of the payload's power system, launch costs can be minimized. The increased interest, however, must be …
View article: InTreeger: An End-to-End Framework for Integer-Only Decision Tree Inference
InTreeger: An End-to-End Framework for Integer-Only Decision Tree Inference Open
Integer quantization has emerged as a critical technique to facilitate deployment on resource-constrained devices. Although they do reduce the complexity of the learning models, their inference performance is often prone to quantization-in…
View article: The online reconfiguration of a distributed on-board computer: The time and network behaviour of a dependable scheduling algorithm
The online reconfiguration of a distributed on-board computer: The time and network behaviour of a dependable scheduling algorithm Open
View article: Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC
Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC Open
RISC-V-based fault-tolerant system-on-chip (SoC) designs are critical for the new generation of automotive and space SoC architectures. However, reliability assessment requires characterization under controlled radiation doses to accuratel…
View article: Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses
Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses Open
International audience
View article: Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes
Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes Open
International audience
View article: Towards Dependable RISC-V Cores for Edge Computing Devices
Towards Dependable RISC-V Cores for Edge Computing Devices Open
The migration of the computation from the cloud into edge devices, i.e., Internet-of-Things (IoTs) devices, reduces the latency and the quantity of data flowing into the network. With the emerging open-source and customizable RISC-V Instru…
View article: An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?
An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds? Open
Fast development, low cost, and reconfigurability are becoming critical factors for aerospace applications, making SRAM FPGAs attractive. However, SRAM FPGAs are prone to errors in the user and on the configuration bits. For their correct …
View article: Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures
Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures Open
Nowadays, various memory-hungry applications like machine learning algorithms are knocking "the memory wall". Toward this, emerging memories featuring computational capacity are foreseen as a promising solution that performs data process i…
View article: Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core Open
Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been developed with the common purpose of protecting circuits against single event…
View article: Preventing Soft Errors and Hardware Trojans in RISC-V Cores
Preventing Soft Errors and Hardware Trojans in RISC-V Cores Open
Soft errors in embedded systems' memories like single-event upsets and multiple-bit upsets lead to data and instruction corruption. Therefore, devices deployed in harsh environments, such as space, use fault-tolerant processors or redundan…
View article: Is RISC-V ready for Space? A Security Perspective
Is RISC-V ready for Space? A Security Perspective Open
Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cor…
View article: Awards Page
Awards Page Open
View article: Introducing the Editorial Board [The Editor’s Desk]
Introducing the Editorial Board [The Editor’s Desk] Open
Professor Xiaoning Jiang serves as Associate Editor-in-Chief in charge of the Spotlight Column. One article is featured in the Spotlight Column, entitled “The First Edition of the World Nanotechnology Marathon: Shifting Paradigms in Teachi…
View article: RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures
RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures Open
Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although processing unit performance has improved over the years, memory capacity has not followed the same tren…
View article: Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability
Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability Open
This paper evaluates the yield of a memristor-based crossbar array of artificial neural networks in the presence of stuck-at-faults (SAFs). A technique based on Markov chains is used to estimate the yield in the presence of stuck-at-faults…
View article: ERIC: An Efficient and Practical Software Obfuscation Framework
ERIC: An Efficient and Practical Software Obfuscation Framework Open
Modern cloud computing systems distribute software executables over a network to keep the software sources, which are typically compiled in a security-critical cluster, secret. We develop ERIC, a new, efficient, and general software obfusc…
View article: Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches Open
The continuous quest for performance pushed processors to incorporate elements such as multiple cores, caches, acceleration units, or speculative execution that make systems very complex. On the other hand, these features often expose unex…
View article: Low power memristive gas sensor architectures with improved sensing accuracy
Low power memristive gas sensor architectures with improved sensing accuracy Open
Memristive devices, traditionally considered for memory, logic, and neuromorphic systems, are exhibiting many interesting properties for applications in a variety of areas, such as in sensing chemicals. However, any realistic approach base…
View article: Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer
Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer Open
View article: Novel Applications Enabled by Memristors [Guest Editorial]
Novel Applications Enabled by Memristors [Guest Editorial] Open
Constant advances in semiconductor manufacturing have led to the ubiquitous presence of cheap and reliable computing devices in all aspects of our lives. However, further innovation exclusively based on scaling the CMOS technology feature …
View article: Neutron irradiated perovskite films and solar cells on PET substrates
Neutron irradiated perovskite films and solar cells on PET substrates Open
View article: 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems - Technical Program
34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems - Technical Program Open
View article: A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses
A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses Open
International audience
View article: DFT 2020 Committees
DFT 2020 Committees Open
View article: Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations
Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations Open
Sensors give factual and process information about the environment or other physical phenomena. Sensing using memristors has been recently introduced for its potential for high density integration and miniaturization. Complementary Resisti…
View article: Yield Estimation of a Memristive Sensor Array
Yield Estimation of a Memristive Sensor Array Open
This paper proposes a method to calculate the yield of a memristor based sensor array considered as the probability that the chip provides acceptable sensing results when the array is affected by manufacturing defects. The modeling is base…
View article: Soft Error Tolerant Count Min Sketches
Soft Error Tolerant Count Min Sketches Open
The estimation of the frequency of the elements on a set is needed in a wide range of computing applications. For example, to estimate the number of hits that a video gets or the number of packets in a network flow. In some cases, the numb…
View article: A Microprocessor Protection Architecture against Hardware Trojans in Memories
A Microprocessor Protection Architecture against Hardware Trojans in Memories Open
Software exploitable Hardware Trojan Horses (HWTs) have been currently inserted in commercial CPUs and, very recently, in memories. Such attacks may allow malicious users to run their own software or to gain unauthorized privileges over th…
View article: Characterization of a RISC-V Microcontroller Through Fault Injection
Characterization of a RISC-V Microcontroller Through Fault Injection Open