Orla Feely
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View article: Generation of a Clocking Signal in Synchronized All-Digital PLL Networks
Generation of a Clocking Signal in Synchronized All-Digital PLL Networks Open
In this brief, we propose a discrete-time framework for the modeling and studying of all-digital phase-locked loop (ADPLL) networks with applications in clock-generating systems. The framework is based on a set of nonlinear stochastic iter…
View article: Semianalytical model for high speed analysis of all-digital PLL clock-generating networks
Semianalytical model for high speed analysis of all-digital PLL clock-generating networks Open
The 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, United States of America, 28-31 May 2017
View article: Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks
Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks Open
International audience
View article: <inline-formula> <tex-math notation="LaTeX">$\Sigma\Delta$</tex-math> </inline-formula> Effects and Charge Locking in Capacitive MEMS Under Dielectric Charge Control
Effects and Charge Locking in Capacitive MEMS Under Dielectric Charge Control Open
This work investigates, analytically and experimentally, the effects induced by the use of a first-order sigma-delta feedback loop as a control method of dielectric charging for capacitive MEMS. This technique allows one to set a desired l…