Omer Khan
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View article: TextPixs: Glyph-Conditioned Diffusion with Character-Aware Attention and OCR-Guided Supervision
TextPixs: Glyph-Conditioned Diffusion with Character-Aware Attention and OCR-Guided Supervision Open
The modern text-to-image diffusion models boom has opened a new era in digital content production as it has proven the previously unseen ability to produce photorealistic and stylistically diverse imagery based on the semantics of natural-…
View article: OPMOS: Ordered Parallel Algorithm for Multi-Objective Shortest-Paths
OPMOS: Ordered Parallel Algorithm for Multi-Objective Shortest-Paths Open
The Multi-Objective Shortest-Path (MOS) problem finds a set of Pareto-optimal solutions from a start node to a destination node in a multi-attribute graph. The literature explores multi-objective A*-style algorithmic approaches to solving …
View article: Author Index
Author Index Open
View article: MaxK-GNN: Extremely Fast GPU Kernel Design for Accelerating Graph Neural Networks Training
MaxK-GNN: Extremely Fast GPU Kernel Design for Accelerating Graph Neural Networks Training Open
In the acceleration of deep neural network training, the GPU has become the mainstream platform. GPUs face substantial challenges on GNNs, such as workload imbalance and memory access irregularities, leading to underutilized hardware. Exis…
View article: Accel-GCN: High-Performance GPU Accelerator Design for Graph Convolution Networks
Accel-GCN: High-Performance GPU Accelerator Design for Graph Convolution Networks Open
Graph Convolutional Networks (GCNs) are pivotal in extracting latent information from graph data across various domains, yet their acceleration on mainstream GPUs is challenged by workload imbalance and memory access irregularity. To addre…
View article: Secure Remote Attestation With Strong Key Insulation Guarantees
Secure Remote Attestation With Strong Key Insulation Guarantees Open
Secure processors with hardware-enforced isolation are crucial for secure cloud computation. However, commercial secure processors have underestimated the capabilities of attackers and failed to provide secure execution environments capabl…
View article: Program Committee
Program Committee Open
View article: ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes
ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes Open
With the ever-increasing virtualization of software and hardware, the privacy of user-sensitive data is a fundamental concern in computation outsourcing. Secure processors enable a trusted execution environment to guarantee security proper…
View article: Towards Real-Time Temporal Graph Learning
Towards Real-Time Temporal Graph Learning Open
In recent years, graph representation learning has gained significant popularity, which aims to generate node embeddings that capture features of graphs. One of the methods to achieve this is employing a technique called random walks that …
View article: Towards Sparsification of Graph Neural Networks
Towards Sparsification of Graph Neural Networks Open
As real-world graphs expand in size, larger GNN models with billions of parameters are deployed. High parameter count in such models makes training and inference on graphs expensive and challenging. To reduce the computational and memory c…
View article: Secure Remote Attestation with Strong Key Insulation Guarantees
Secure Remote Attestation with Strong Key Insulation Guarantees Open
Recent years have witnessed a trend of secure processor design in both academia and industry. Secure processors with hardware-enforced isolation can be a solid foundation of cloud computation in the future. However, due to recent side-chan…
View article: HD-CPS: Hardware-assisted Drift-aware Concurrent Priority Scheduler for Shared Memory Multicores
HD-CPS: Hardware-assisted Drift-aware Concurrent Priority Scheduler for Shared Memory Multicores Open
Efficiently exploiting parallelism remains a challenging problem in multicore processors. For many algorithms, executing tasks in some priority order results in a work efficient execution. However, searching high-priority tasks requires co…
View article: HD-CPS: Hardware-assisted Drift-aware Concurrent Priority Scheduler for Shared Memory Multicores
HD-CPS: Hardware-assisted Drift-aware Concurrent Priority Scheduler for Shared Memory Multicores Open
Efficiently exploiting parallelism remains a challenging problem in multicore processors. For many algorithms, executing tasks in some priority order results in a work efficient execution. However, searching high-priority tasks requires co…
View article: Message from the General Chairs
Message from the General Chairs Open
On behalf of the organizing committee, we are pleased to welcome you to the 17th IEEE International Symposium on Workload Characterization (IISWC-2021), conducted virtually from November 7-9, 2021. IISWC is a premier international forum fo…
View article: PRISM
PRISM Open
Multicores increasingly deploy safety-critical parallel applications that demand resiliency against soft-errors to satisfy the safety standards. However, protection against these errors is challenging due to complex communication and data …
View article: External Review Committee
External Review Committee Open
View article: Knowledge Management: Document Similarity Based Recommendation
Knowledge Management: Document Similarity Based Recommendation Open
Futurice works on developing and designing digital services and products. Its an innovative organization which invests its expertise and experience in promoting and creating a knowledge management system powered by data and artificial inte…
View article: Program Committee : IISWC 2020
Program Committee : IISWC 2020 Open
View article: Program Committee
Program Committee Open
View article: Accelerating relax-ordered task-parallel workloads using multi-level dependency checking
Accelerating relax-ordered task-parallel workloads using multi-level dependency checking Open
Work-efficient task-parallel algorithms enforce ordered execution of tasks using priority schedulers. These algorithms suffer from limited parallelism due to data movement and synchronization bottlenecks. State-of-the-art priority schedule…
View article: Exploring accelerator and parallel graph algorithmic choices for temporal graphs
Exploring accelerator and parallel graph algorithmic choices for temporal graphs Open
Many real-world systems utilize graphs that are time-varying in nature, where edges appear and disappear with respect to time. Moreover, the weights of different edges are also a function of time. Various conventional graph algorithms, suc…
View article: Program Committee
Program Committee Open
View article: IRONHIDE: A Secure Multicore that Efficiently Mitigates Microarchitecture State Attacks for Interactive Applications
IRONHIDE: A Secure Multicore that Efficiently Mitigates Microarchitecture State Attacks for Interactive Applications Open
Microprocessors enable aggressive hardware virtualization by means of which multiple processes temporally execute on the system. These security-critical and ordinary processes interact with each other to assure application progress. Howeve…
View article: IRONHIDE: A Secure Multicore that Efficiently Mitigates\n Microarchitecture State Attacks for Interactive Applications
IRONHIDE: A Secure Multicore that Efficiently Mitigates\n Microarchitecture State Attacks for Interactive Applications Open
Microprocessors enable aggressive hardware virtualization by means of which\nmultiple processes temporally execute on the system. These security-critical\nand ordinary processes interact with each other to assure application progress.\nHow…
View article: IRONHIDE: A Secure Multicore Architecture that Leverages Hardware Isolation Against Microarchitecture State Attacks.
IRONHIDE: A Secure Multicore Architecture that Leverages Hardware Isolation Against Microarchitecture State Attacks. Open
Modern microprocessors enable aggressive hardware virtualization that exposes the microarchitecture state of the processor due to temporal sharing of hardware resources. This paper proposes a novel secure multicore architecture, IRONHIDE t…
View article: Guest Editors Introduction: Special Section on Emerging Technologies in Computer Design
Guest Editors Introduction: Special Section on Emerging Technologies in Computer Design Open
The papers in this special section were presented at the IEEE International Conference on Computer Design (ICCD).
View article: Accelerating Synchronization Using Moving Compute to Data Model at 1,000-core Multicore Scale
Accelerating Synchronization Using Moving Compute to Data Model at 1,000-core Multicore Scale Open
Thread synchronization using shared memory hardware cache coherence paradigm is prevalent in multicore processors. However, as the number of cores increase on a chip, cache line ping-pong prevents performance scaling for algorithms that de…
View article: Declarative Resilience
Declarative Resilience Open
To protect multicores from soft-error perturbations, research has explored various resiliency schemes that provide high soft-error coverage. However, these schemes incur high performance and energy overheads. We observe that not all soft-e…
View article: Exploiting the Tradeoff between Program Accuracy and Soft-error Resiliency Overhead for Machine Learning Workloads
Exploiting the Tradeoff between Program Accuracy and Soft-error Resiliency Overhead for Machine Learning Workloads Open
To protect multicores from soft-error perturbations, resiliency schemes have been developed with high coverage but high power and performance overheads. Emerging safety-critical machine learning applications are increasingly being deployed…
View article: Revisiting Definitional Foundations of Oblivious RAM for Secure Processor Implementations
Revisiting Definitional Foundations of Oblivious RAM for Secure Processor Implementations Open
Oblivious RAM (ORAM) is a renowned technique to hide the access patterns of an application to an untrusted memory. According to the standard ORAM definition presented by Goldreich and Ostrovsky, two ORAM access sequences must be computatio…