Olivier Sentieys
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View article: Side-Channel Extraction of Dataflow AI Accelerator Hardware Parameters
Side-Channel Extraction of Dataflow AI Accelerator Hardware Parameters Open
Dataflow neural network accelerators efficiently process AI tasks on FPGAs, with deployment simplified by ready-to-use frameworks and pre-trained models. However, this convenience makes them vulnerable to malicious actors seeking to revers…
View article: A Hard-Label Cryptanalytic Extraction of Non-Fully Connected Deep Neural Networks using Side-Channel Attacks
A Hard-Label Cryptanalytic Extraction of Non-Fully Connected Deep Neural Networks using Side-Channel Attacks Open
During the past decade, Deep Neural Networks (DNNs) proved their value on a large variety of subjects. However despite their high value and public accessibility, the protection of the intellectual property of DNNs is still an issue and an …
View article: MaxiMals: A Low-cost Hardening Technique for Large Vision Transformers
MaxiMals: A Low-cost Hardening Technique for Large Vision Transformers Open
International audience
View article: Combining Weight Approximation, Sharing and Retraining for Neural Network Model Compression
Combining Weight Approximation, Sharing and Retraining for Neural Network Model Compression Open
Neural network model compression is very important to achieve model deployment based on the memory and storage available in different computing systems. Generally, the continuous drive for higher accuracy in these models increases their si…
View article: A Hardware Instruction Generation Mechanism for Energy-Efficient Computational Memories
A Hardware Instruction Generation Mechanism for Energy-Efficient Computational Memories Open
International audience
View article: Lightweight Hardware-Based Cache Side-Channel Attack Detection for Edge Devices (Edge-CaSCADe)
Lightweight Hardware-Based Cache Side-Channel Attack Detection for Edge Devices (Edge-CaSCADe) Open
Cache Side-Channel Attacks (CSCAs) have been haunting most processor architectures for decades now. Existing approaches to mitigation of such attacks have certain drawbacks, namely software mishandling, performance overhead, and low throug…
View article: AdaQAT: Adaptive Bit-Width Quantization-Aware Training
AdaQAT: Adaptive Bit-Width Quantization-Aware Training Open
Large-scale deep neural networks (DNNs) have achieved remarkable success in many application scenarios. However, high computational complexity and energy costs of modern DNNs make their deployment on edge devices challenging. Model quantiz…
View article: A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training
A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training Open
Training Deep Neural Networks (DNNs) can be computationally demanding, particularly when dealing with large models. Recent work has aimed to mitigate this computational challenge by introducing 8-bit floating-point (FP8) formats for multip…
View article: Impact of High-Level Synthesis on Reliability of Artificial Neural Network Hardware Accelerators
Impact of High-Level Synthesis on Reliability of Artificial Neural Network Hardware Accelerators Open
International audience
View article: On-board Payload Data Processing Combined with the Roofline Model for Hardware/Software Design
On-board Payload Data Processing Combined with the Roofline Model for Hardware/Software Design Open
International audience
View article: Characterizing and Modeling Synchronous Clock-Glitch Fault Injection
Characterizing and Modeling Synchronous Clock-Glitch Fault Injection Open
View article: When Side-Channel Attacks Break the Black-Box Property of Embedded Artificial Intelligence
When Side-Channel Attacks Break the Black-Box Property of Embedded Artificial Intelligence Open
Artificial intelligence, and specifically deep neural networks (DNNs), has rapidly emerged in the past decade as the standard for several tasks from specific advertising to object detection. The performance offered has led DNN algorithms t…
View article: High-Level Synthesis-Based On-board Payload Data Processing considering the Roofline Model
High-Level Synthesis-Based On-board Payload Data Processing considering the Roofline Model Open
International audience
View article: Neutron-Induced Error Rate of Vision Transformer Models on GPUs
Neutron-Induced Error Rate of Vision Transformer Models on GPUs Open
International audience
View article: Lossless Neural Network Model Compression Through Exponent Sharing
Lossless Neural Network Model Compression Through Exponent Sharing Open
International audience
View article: Reliability evaluation of Convolutional Neural Network's basic operations on a RISC-V processor
Reliability evaluation of Convolutional Neural Network's basic operations on a RISC-V processor Open
International audience
View article: Impact of High-Level-Synthesis on Reliability of Neural Network Hardware Accelerators
Impact of High-Level-Synthesis on Reliability of Neural Network Hardware Accelerators Open
International audience
View article: Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors
Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors Open
International audience
View article: A machine-learning-guided framework for fault-tolerant DNNs
A machine-learning-guided framework for fault-tolerant DNNs Open
International audience
View article: Impact of Transient Faults on Timing Behavior and Mitigation with Near-Zero WCET Overhead
Impact of Transient Faults on Timing Behavior and Mitigation with Near-Zero WCET Overhead Open
As time-critical systems require timing guarantees, Worst-Case Execution Times (WCET) have to be employed. However, WCET estimation methods usually assume fault-free hardware. If proper actions are not taken, such fault-free WCET approache…
View article: Customizing Number Representation and Precision
Customizing Number Representation and Precision Open
There is a growing interest in the use of reduced-precision arithmetic, exacerbated by the recent interest in artificial intelligence, especially with deep learning. Most architectures already provide reduced-precision capabilities (e.g., …
View article: Characterizing a Neutron-Induced Fault Model for Deep Neural Networks
Characterizing a Neutron-Induced Fault Model for Deep Neural Networks Open
The reliability evaluation of deep neural networks (DNNs) executed on graphic processing units (GPUs) is a challenging problem, since the hardware architecture is highly complex, and the software frameworks are composed of many layers of a…
View article: Characterizing a Neutron-Induced Fault Model for Deep Neural Networks
Characterizing a Neutron-Induced Fault Model for Deep Neural Networks Open
The reliability evaluation of Deep Neural Networks (DNNs) executed on Graphic Processing Units (GPUs) is a challenging problem since the hardware architecture is highly complex and the software frameworks are composed of many layers of abs…
View article: Approximation-Aware Task Deployment on Heterogeneous Multicore Platforms With DVFS
Approximation-Aware Task Deployment on Heterogeneous Multicore Platforms With DVFS Open
International audience
View article: Functional and Timing Implications of Transient Faults in Critical Systems
Functional and Timing Implications of Transient Faults in Critical Systems Open
Embedded systems in critical domains, such as auto-motive, aviation, space domains, are often required to guarantee both functional and temporal correctness. Considering transient faults, fault analysis and mitigation approaches are implem…
View article: Functional and Timing Implications of Transient Faults in Critical Systems
Functional and Timing Implications of Transient Faults in Critical Systems Open
International audience
View article: Characterizing Deep Neural Networks Neutrons-Induced Error Model
Characterizing Deep Neural Networks Neutrons-Induced Error Model Open
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View article: Experimental evaluation of neutron-induced errors on a multicore RISC-V platform
Experimental evaluation of neutron-induced errors on a multicore RISC-V platform Open
RISC-V architectures have gained importance in the last years due to their flexibility and open-source Instruction Set Architecture (ISA), allowing developers to efficiently adopt RISC-V processors in several domains with a reduced cost. F…
View article: Experimental evaluation of neutron-induced errors on a multicore RISC-V\n platform
Experimental evaluation of neutron-induced errors on a multicore RISC-V\n platform Open
RISC-V architectures have gained importance in the last years due to their\nflexibility and open-source Instruction Set Architecture (ISA), allowing\ndevelopers to efficiently adopt RISC-V processors in several domains with a\nreduced cost…
View article: Disentangled Loss for Low-Bit Quantization-Aware Training
Disentangled Loss for Low-Bit Quantization-Aware Training Open
International audience