Patrick Vuillod
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View article: Improving LUT-based optimization for ASICs
Improving LUT-based optimization for ASICs Open
LUT-based optimization techniques are finding new applications in synthesis of ASIC designs. Intuitively, packing logic into LUTs provides a better balance between functionality and structure in logic optimization. On this basis, the LUT-e…
View article: Majority-based Design Flow for AQFP Superconducting Family
Majority-based Design Flow for AQFP Superconducting Family Open
Adiabatic superconducting devices are promising candidates to develop high-speed/low-power electronics. Advances in physical technology must be matched with a systematic development of comprehensive design and simulation tools to bring sup…
View article: LUT-Based Optimization For ASIC Design Flow
LUT-Based Optimization For ASIC Design Flow Open
In this paper, we develop a new LUT-based optimization flow tailored for the synthesis of ASICs rather than FPGAs. We enhance LUT-mapping to consider the literal/AIG cost of LUT-nodes. We extend traditional Boolean methods to simplify and …
View article: SAT-Sweeping Enhanced for Logic Synthesis
SAT-Sweeping Enhanced for Logic Synthesis Open
SAT-sweeping is a powerful method for simplifying logic networks. It consists of merging gates that are proven equivalent (up to complementation) by running simulation and SAT solving in synergy. SAT-sweeping is used in both verification a…
View article: Extending Boolean Methods for Scalable Logic Synthesis
Extending Boolean Methods for Scalable Logic Synthesis Open
In recent years, Boolean methods in logic synthesis have been drawing the attention of EDA researchers due to the continuous push to advance quality of results. Boolean methods require high computational cost, as they rely on complete func…
View article: Scalable Boolean Methods in a Modern Synthesis Flow
Scalable Boolean Methods in a Modern Synthesis Flow Open
With the continuous push to improve Quality of Results (QoR) in EDA, Boolean methods in logic synthesis have been recently drawing the attention of researchers. Boolean methods achieve better QoR than algebraic methods but require higher c…
View article: Integrated ESOP Refactoring for Industrial Designs
Integrated ESOP Refactoring for Industrial Designs Open
We present a multi-level logic refactoring algorithm based on exclusive sum-of-product (ESOP) expressions. ESOP expressions are two-level logic representation forms, similar to sum of -product (SOP) expressions. However, ESOPs use EXOR ins…
View article: Improvements to boolean resynthesis
Improvements to boolean resynthesis Open
In electronic design automation Boolean resynthesis techniques are increasingly used to improve the quality of results where algebraic methods hit local minima Boolean methods rely on complete functional properties of a logic circuit, pref…
View article: Enabling exact delay synthesis
Enabling exact delay synthesis Open
Given (i) a Boolean function, (ii) a set of arrival times at the inputs, and (iii) a gate library with associated delay values, the exact delay synthesis problem asks for a circuit implementation which minimizes the arrival time at the out…
View article: Multi-level logic benchmarks: An exactness study
Multi-level logic benchmarks: An exactness study Open
In this paper, we study exact multi-level logic benchmarks. We refer to an exact logic benchmark, or exact benchmark in short, as the optimal implementation of a given Boolean function, in terms of minimum number of logic levels and/or nod…