Ramin Rajaei
YOU?
Author Swipe
View article: Addressing Benign and Malicious Crosstalk in Modern System-on-Chips
Addressing Benign and Malicious Crosstalk in Modern System-on-Chips Open
In this study, we investigate the effects of intentional crosstalk noise on modern Multi-Processor System-on-Chips (MPSoCs). We demonstrate the potential for an adversary to inject false data into the communication network of the MPSoC, th…
View article: Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories
Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories Open
The memory wall bottleneck is a key challenge across many data-intensive applications. Multi-level FeFET-based embedded non-volatile memories are a promising solution for denser and more energy-efficient on-chip memory. However, reliable m…
View article: In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories
In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories Open
Nearest neighbor (NN) search is an essential operation in many applications, such as one/few-shot learning and image classification. As such, fast and low-energy hardware support for accurate NN search is highly desirable. Ternary content-…
View article: A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training and Inference
A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training and Inference Open
An analog synapse circuit based on ferroelectric-metal field-effect transistors is proposed, that offers 6-bit weight precision. The circuit is comprised of volatile least significant bits (LSBs) used solely during training, and non-volati…
View article: A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training\n and Inference
A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training\n and Inference Open
An analog synapse circuit based on ferroelectric-metal field-effect\ntransistors is proposed, that offers 6-bit weight precision. The circuit is\ncomprised of volatile least significant bits (LSBs) used solely during\ntraining, and non-vol…
View article: Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology
Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology Open
In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs). Moreover, they show a hi…
View article: A Novel Radiation Hardened Parallel IO Port for Highly Reliable Digital IC Design
A Novel Radiation Hardened Parallel IO Port for Highly Reliable Digital IC Design Open
This article proposes a radiation hardened parallel IO port capable of tolerating radiation induced soft errors including single event upsets (SEUs) as well as single event transients (SETs).To investigate the soft error tolerance capabili…
View article: Design of a Radiation Hardened Register File for Highly Reliable Microprocessors
Design of a Radiation Hardened Register File for Highly Reliable Microprocessors Open
In this paper, a powerful bit upset masking (PBUM) technique for design of a high reliable register file is proposed.This technique is based on the triple modular redundancy (TMR) technique with the key capability of double faulty bit mask…