Rogier Baert
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View article: Cell-Aware Test on Various Circuits in an Advanced 3-nm Technology
Cell-Aware Test on Various Circuits in an Advanced 3-nm Technology Open
Editor's notes: This article describes a method to improve test quality by explicitly targeting realistic cell-internal open and short defects through dedicated technology cell-level test patterns. The authors report some of the earliest r…
View article: IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and μ- & n- TSVs
IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and μ- & n- TSVs Open
info:eu-repo/semantics/published
View article: 3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes
3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes Open
We present local global SRAM macro optimizations for 3nm FinFET and 2nm Nanosheet using Face-to-Face (F2F) and Wafer-to-Wafer (W2W) hybrid bonding at sub 1um pitch. Bonding pad parasitics are measured experimentally to calibrate RC models …
View article: Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI
Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI Open
© 2018 IEEE. Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNF…