Explanipedia

Enhancing sugarcane leaf disease classification using vision transformers over CNNs Open

Sandeep Miryala, Krupa Rasane · 2025

Sugarcane is a globally significant crop facing threats from leaf diseases that impact its productivity. Traditional detection methods are often inefficient and time-consuming. This study explores the use of Vision Transformers (ViT) for c…

Performance characterization of 5×5×12 mm3 virtual Frisch-grid TlBr detectors Open

A. E. Bolotnikov, Conner Brown, G. Carini, James F. Christian, L. Cirignano , et al. · 2025

RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades Open

G. Alimonti, A. Andreazza, Fernando Arteche, M. Barbero, P. Barrillon , et al. · 2025

The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × 50 μm 2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been de…

ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade Open

X. Huang, Quan Sun, D. T. Gong, Piljun Gwak, D. Kim , et al. · 2024

We present the design and characterization of the first full chain precision timing prototype ASIC, named ETL Readout Chip version 1 (ETROC1) for the CMS MTD endcap timing layer (ETL) upgrade. The ETL utilizes Low Gain Avalanche Diode (LGA…

ETROC1: The First Full Chain Precision Timing Prototype ASIC for CMS MTD Endcap Timing Layer Upgrade Open

X. Huang, Quan Sun, Datao Gong, Piljun Gwak, Doyeong Kim , et al. · 2024

We present the design and characterization of the first full chain precision timing prototype ASIC, named ETL Readout Chip version 1 (ETROC1) for the CMS MTD endcap timing layer (ETL) upgrade. The ETL utilizes Low Gain Avalanche Diode (LGA…

Using 3D position sensitivity to reveal response non-uniformities in CdZnTe, TlBr, and CsPbBr3 detectors Open

A. E. Bolotnikov, Conner Brown, G. Carini, James F. Christian, L. Cirignano , et al. · 2023

Soft error-mitigating semiconductor design system and associated methods Open

Sandeep Miryala, J. Hoff, G. Deptuch · 2023

A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage element…

A low-power 1 Gb/s line driver with configurable pre-emphasis for lossy transmission lines Open

Nicholas St. John, Soumyajit Mandal, Sandeep Miryala, P. Maj, G. Deptuch , et al. · 2023

A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization architecture. The relative delays between the taps are selectable in increments of 1/16th of the…

Investigation of Timing Properties for an Event Driven with Access and Reset Decoder Readout Architecture for a Pixel Array Open

D. Górni, G. Deptuch, Sandeep Miryala · 2022

The large number of data generating sources (data channels) on a single chip requires appropriate techniques to manage a readout from these channels. One of the main methods is sharing a medium of transmission, which requires arbitration t…

Smart sensors using artificial intelligence for on-detector electronics and ASICs Open

G. Carini, G. Deptuch, J. Dickinson, D. Doering, A. Dragone , et al. · 2022

Cutting edge detectors push sensing technology by further improving spatial and temporal resolution, increasing detector area and volume, and generally reducing backgrounds and noise. This has led to a explosion of more and more data being…

Design and Challenges of Edge Computing ASICs on Front-End Electronics Open

Sandeep Miryala, G. Carini, G. Deptuch, Jin Huang, Srinivas Katkoori , et al. · 2022

In situ or hardware-embedded data processing of raw signals, close to their source, in radiation detectors is expected to provide dramatic improvements in data quality and volumes. However, the implementation of artificial neural networks …

Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific Applications Open

Sandeep Miryala, Md Adnan Zaman, Sandeep S. Mittal, Yihui Ren, G. Deptuch , et al. · 2022

High data rate detectors play an integral part in scientific research and their development is actively pursued at High Energy Physics (HEP) facilities around the world. Edge Machine Learning (ML) offers the ability to reduce data rates by…

Event driven readout architecture with non-priority arbitration for radiation detectors Open

D. Górni, G. Deptuch, Sandeep Miryala, D. P. Siddons, A. Kuczewski , et al. · 2022

A novel event driven readout architecture, EDWARD (Event Driven with Access and Reset Decoder) architecture, for highly granular pixel detectors is presented. It incorporates, inter alia, an asynchronous arbitration tree based on Seitz’ ar…

Multi-channel front-end ASIC for a 3D position-sensitive detector Open

G. Pinaroli, Sven Herrmann, Sandeep Miryala, Vamshi Manthena, G. Deptuch , et al. · 2022

Arrays of 3D position-sensitive detectors (3DPSD), operating at room temperature and using cadmium zinc telluride (CZT) and thallium bromide (TIBr) sensors, are suitable for gamma-ray spectrometry in many applications. One detector configu…

The COLDATA Concentrator ASIC for the Deep Underground Neutrino Experiment [Poster] Open

Jim Hoff, D. Braga, David Cristian, S. Holm, Sandeep Miryala , et al. · 2022

(DUNE) will detect a broadband neutrino beam from Fermilab in an underground massive liquid argon time-projection chamber at an L/E of about 103 km GeV-1 to reach good sensitivity for CP-phase measurements and the determination of the mass…

Waveform processing using neural network algorithms on the front-end electronics Open

Sandeep Miryala, Saurabh Mittal, Yihui Ren, G. Carini, G. Deptuch , et al. · 2022

In a multi-channel radiation detector readout system, waveform sampling, digitization, and raw data transmission to the data acquisition system constitute a conventional processing chain. The deposited energy on the sensor is estimated by …

ColdADC_P2: A 16-Channel Cryogenic ADC ASIC for the Deep Underground Neutrino Experiment Open

Carl Grace, D. Braga, H. Chen, D. Christian, M. Dabrowski , et al. · 2021

The second and final version of ColdADC, called ColdADC_P2, is presented. ColdADC_P2 is a 16-channel, 12-bit, 2 MS/s digitizer application-specific integrated circuit (ASIC) intended for use inside the DUNE Far Detector. ColdADC_P2 contain…

Real-time data reduction at 100 Tbps: Challenge and opportunity for AI-based data reduction for next-generation large-scale nuclear physics collider experiment Open

Jin Huang, M. X. Liu, Sandeep Miryala, Yihui Ren · 2021

The modern large-scale nuclear physics (NP) experiments in high-energy particle colliders utilize streaming-readout electronics to digitize detector response at O(100) Tbps bandwidth. Prominent examples at Brookhaven National Lab (BNL) inc…

Characterization and QC practice of 16-channel ADC ASIC at cryogenic temperature for Liquid Argon TPC front-end readout electronics system in DUNE experiment Open

Edoardo Lopriore, D. Braga, H. Chen, D. Christian, M. Dabrowski , et al. · 2021

ColdADC is a low-noise 16-channel analog-to-digital converter ASIC designed for cold readout electronics of Liquid Argon Time Projection Chambers (LArTPCs) in the Deep Underground Neutrino Experiment (DUNE). ColdADC was specifically design…

An injectable self-healing anesthetic glycolipid-based oleogel with antibiofilm and diabetic wound skin repair properties Open

Yadavali Siva Prasad, Sandeep Miryala, Krishnamoorthy Lalitha, B. Saritha, C. Uma Maheswari , et al. · 2020

Globally, wound infections are considered as one of the major healthcare problems owing to the delayed healing process in diabetic patients and microbial contamination. Thus, the development of advanced materials for wound skin repair is o…

ETROC1 Design Note. Version 1.0 Open

Christopher Edwards, D. Gong, Xing Huang, Kent Liu, Ted Liu , et al. · 2020

This document provides the relevant information needed during ETROC1 design integration stage, and it is now improved to be used as a guide for testing ETROC1 prototype chips.

Supramolecular gels of gluconamides derived from renewable resources: Antibacterial and anti‐biofilm applications Open

Yadavali Siva Prasad, S. Manikandan, Krishnamoorthy Lalitha, Sandeep Miryala, Rebaka Vara Prasad , et al. · 2020

Carbohydrates are versatile materials widely used for several applications including food, pharmaceuticals, cosmetics, and drug delivery systems due to their inherent properties such as non‐toxicity, biodegradability, and bio‐compatibility…

CDP1—A Data Concentrator Prototype for the Deep Underground Neutrino Experiment Open

Sandeep Miryala, D. Braga, D. Christian, G. Deptuch, Ping Gui , et al. · 2019

The design, power analysis and tests of a first COLDATA Prototype (CDP1) design in 65nm process for the Long Baseline Neutrino Facility (LBNF) and the Deep Underground Neutrino Experiment (DUNE) are presented here. CDP1 is a prototype ASIC…

The ETROC Project: Precision Timing ASIC Development for LGAD-based CMS Endcap Timing Layer (ETL) Upgrade Open

Tiehui Liu, G. Deptuch, S. Łoś, Sandeep Miryala, J. Olsen , et al. · 2019

The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD silicon …

RD53A: a large scale prototype for HL-LHC silicon pixel detector phase 2 upgrades Open

Ennio Monteil, M. Barbero, D. Fougeron, S. Godiot, M. Ménouni , et al. · 2019

The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme require- ments, such as: 50x50 μm pixels, high rate (3 GHz/cm2), unprecedented radiation levels (1 Grad), high readout speed and serial powering. As a co…

Characterization of Soft Error Rate Against Memory Elements Spacing and Clock Skew in a Logic with Triple Modular Redundancy in a 65nm Process Open

Sandeep Miryala, T. Hemperek, M. Menouni · 2019

Single Event Effects introduce soft errors in ASICs. Design methodologies like Triple ModularRedundancy (TMR) with clock skew insertion, a system level redundancy technique is a commonpractice by designers to mitigate soft errors. However,…

Quantum Sensing for High Energy Physics Open

Zeeshan Ahmed, Yuri Alexeev, G. Apollinari, Asimina Arvanitaki, D. D. Awschalom , et al. · 2018

Report of the first workshop to identify approaches and techniques in the domain of quantum sensing that can be utilized by future High Energy Physics applications to further the scientific goals of High Energy Physics.

Development of a Large Pixel Chip Demonstrator in RD53 for ATLAS and CMS Upgrades Open

E. Conti, M. Barbero, Denis Fougeron, S. Godiot, M. Menouni , et al. · 2018

RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It…

Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip Open

L.M. Jara Casas, D. Ceresa, S. Kulis, Sandeep Miryala, J. Christiansen , et al. · 2017

A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of stand…

The VeloPix ASIC Open

T. Poikela, R. Ballabriga, J. Buytaert, X. Llopart, W. Wong , et al. · 2017

VeloPix, a 130 nm CMOS technology chip with data driven and zero suppressed readout, will be used as a readout chip for the hybrid pixel system of the LHCb Vertex Locator (VELO) upgrade. The upgrade, scheduled for LHC Run-3, will enable th…

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