Lawrence T. Clark
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View article: Secure true random number generation using 1.5-T transistor flash memory
Secure true random number generation using 1.5-T transistor flash memory Open
This disclosure relates generally to physically unclonable function (PUF) circuitry along with methods of generating numbers. In one embodiment, the PUF circuitry includes a memory, a memory control circuitry, and whitening circuitry. To r…
View article: Sequential circuit design for radiation hardened multiple voltage integrated circuits
Sequential circuit design for radiation hardened multiple voltage integrated circuits Open
The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operatin…
View article: ASAP5: A predictive PDK for the 5 nm node
ASAP5: A predictive PDK for the 5 nm node Open
We present a predictive process design kit (PDK) for the 5 nm technology node, the ASAP5 PDK. ASAP5 is not related to a particular foundry and the assumptions are derived from literature. It incorporates several innovations that the semico…
View article: Single Event Upset Response of 12L FinFET Digital Circuits.
Single Event Upset Response of 12L FinFET Digital Circuits. Open
the expected orbital bit-errors/day were simulated to be approximately 70% lower with the IMC shift register. These measured results help demonstrate the efficacy of using the IMC device as a low-cost means for improving the SEE radiation …
View article: Measuring and Modeling Single Event Transients in 12-nm Inverters
Measuring and Modeling Single Event Transients in 12-nm Inverters Open
In this article, we present a unique method of measuring single-event transient (SET) sensitivity in 12-nm FinFET technology. A test structure is presented that approximately measures the length of SETs using flip-flop shift registers with…
View article: Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors
Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors Open
Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally in…
View article: ASAP7: A 7-nm finFET predictive process design kit
ASAP7: A 7-nm finFET predictive process design kit Open
We describe a 7-nm predictive process design kit (PDK) called the ASAP7 PDK, developed in collaboration with ARM Ltd. for academic use. The PDK is realistic, based on current assumptions for the 7-nm technology node, but is not tied to any…
View article: Radiation Hardened Electronics Destined For Severe Nuclear Reactor Environments
Radiation Hardened Electronics Destined For Severe Nuclear Reactor Environments Open
Post nuclear accident conditions represent a harsh environment for electronics. The full station blackout experience at Fukushima shows the necessity for emergency sensing capabilities in a radiation-enhanced environment. This NEET (Nuclea…
View article: Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014)
Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014) Open
The papers in this special section consists of expanded versions of six papers presented at the Custom Integrated Circuits Conference (CICC), held in San Jose, CA, USA, in September 2014.