Tianming Ni
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Author Swipe
View article: Comparative Study of a Modified Suture Technique with a Minimal Renal Pelvis Incision in Paediatric Hydronephrosis Treatment
Comparative Study of a Modified Suture Technique with a Minimal Renal Pelvis Incision in Paediatric Hydronephrosis Treatment Open
Background Laparoscopic pyeloplasty (LP) is an effective treatment for ureteropelvic junction obstruction (UPJO), but research on reducing renal pelvis incision size and improving suture techniques is limited. Purpose To compare LP with a …
View article: Compact fully-unrolled architectures for AES based on merging and combining of linear operations
Compact fully-unrolled architectures for AES based on merging and combining of linear operations Open
View article: A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faults
A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faults Open
Silent Data Errors (SDEs) from time-zero defects and aging degrade safety-critical systems. Functional testing detects SDE-related faults but is expensive to simulate. We present a unified spatio-temporal graph convolutional network (ST-GC…
View article: Nonvolatile Double- and Triple-Node-Upset Tolerant Latch Designs Based on FeFET and CMOS
Nonvolatile Double- and Triple-Node-Upset Tolerant Latch Designs Based on FeFET and CMOS Open
International audience
View article: Design of Nonvolatile and Multinode-Upset Recoverable Latches Based on Magnetic Tunnel Junction and CMOS
Design of Nonvolatile and Multinode-Upset Recoverable Latches Based on Magnetic Tunnel Junction and CMOS Open
International audience
View article: Cost-Optimized Double-Node-Upset-Recovery Latch Designs With Aging Mitigation and Algorithm-Based Verification for Long-Term Robustness Enhancement
Cost-Optimized Double-Node-Upset-Recovery Latch Designs With Aging Mitigation and Algorithm-Based Verification for Long-Term Robustness Enhancement Open
International audience
View article: SASL-JTAG+: An Enhanced Lightweight and Secure JTAG Authentication Mechanism for IoT Systems with Diverse Devices
SASL-JTAG+: An Enhanced Lightweight and Secure JTAG Authentication Mechanism for IoT Systems with Diverse Devices Open
View article: Cost-Optimized and Highly Robust Latches Providing Complete Quadruple-Node-Upset Tolerance and Recovery With Algorithm-Based Verifications
Cost-Optimized and Highly Robust Latches Providing Complete Quadruple-Node-Upset Tolerance and Recovery With Algorithm-Based Verifications Open
International audience
View article: Compact Fully-Unrolled Architectures for Aes Based on Merging and Combining of Linear Operations
Compact Fully-Unrolled Architectures for Aes Based on Merging and Combining of Linear Operations Open
View article: Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications
Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications Open
International audience
View article: IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications
IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications Open
International audience
View article: MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method
MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method Open
International audience
View article: A Lightweight General Puf Framework for Resisting Machine Learning Attacks
A Lightweight General Puf Framework for Resisting Machine Learning Attacks Open
View article: High-Performance Low-Cost Triple-Node-Upset Self-Recovery Latch Designs for Radiation Environment
High-Performance Low-Cost Triple-Node-Upset Self-Recovery Latch Designs for Radiation Environment Open
View article: Nvsrl: A Fefet-Based Non-Volatile and Seu-Recoverable Latch Design
Nvsrl: A Fefet-Based Non-Volatile and Seu-Recoverable Latch Design Open
View article: A Demultiplexer-Based Dual-Path Switching True Random Number Generator
A Demultiplexer-Based Dual-Path Switching True Random Number Generator Open
View article: FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell
FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell Open
International audience
View article: Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS Open
International audience
View article: Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors
Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors Open
Given its advantageous power- and area-efficiency characteristics and its compatibility with traditional CMOS technology, the memristor has emerged as a promising candidate for low-power applications. To leverage these capacities, a new ed…
View article: Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications
Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications Open
International audience
View article: A Low Overhead and Double-Node-Upset Self-Recoverable Latch
A Low Overhead and Double-Node-Upset Self-Recoverable Latch Open
International audience
View article: Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications
Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications Open
International audience
View article: Memristor-Based D-Flip-Flop Design and Application in Built-In Self-Test
Memristor-Based D-Flip-Flop Design and Application in Built-In Self-Test Open
There are several significant advantages of memristors, such as their nano scale, fast switching speed, power efficiency and compatibility with CMOS technology, as one of the alternatives in the next generation of semiconductor storage dev…
View article: A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications
A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications Open
International audience
View article: Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata
Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata Open
International audience
View article: Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments
Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments Open
International audience
View article: LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments
LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments Open
International audience
View article: Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS
Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS Open
International audience
View article: A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology
A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology Open
International audience
View article: Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications
Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications Open
International audience