Timothy Roscoe
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View article: Mainframe-Style Channel Controllers for Modern Disaggregated Memory Systems
Mainframe-Style Channel Controllers for Modern Disaggregated Memory Systems Open
Despite the promise of alleviating the main memory bottleneck, and the existence of commercial hardware implementations, techniques for Near-Data Processing have seen relatively little real-world deployment. The idea has received renewed i…
View article: CCKit: An open-source toolkit for cache coherent accelerators
CCKit: An open-source toolkit for cache coherent accelerators Open
The trend towards system specialization is leading to a proliferation of accelerators, exposing interconnects as serious bottlenecks, both in functionality and performance. As a result, several alternative approaches have been proposed whi…
View article: Function as a Function
Function as a Function Open
Function as a Service (FaaS) and the associated serverless computing paradigm alleviates users from resource management and allows cloud platforms to optimize system infrastructure under the hood. Despite significant advances, FaaS infrast…
View article: Putting out the hardware dumpster fire
Putting out the hardware dumpster fire Open
The immense hardware complexity of modern computers, both mobile phones and datacenter servers, is a seemingly endless source of bugs and vulnerabilities in system software.
View article: ECI: a Customizable Cache Coherency Stack for Hybrid FPGA-CPU Architectures
ECI: a Customizable Cache Coherency Stack for Hybrid FPGA-CPU Architectures Open
Unlike other accelerators, FPGAs are capable of supporting cache coherency, thereby turning them into a more powerful architectural option than just a peripheral accelerator. However, most existing deployments of FPGAs are either non-cache…
View article: Generating correct initial page tables from formal hardware descriptions
Generating correct initial page tables from formal hardware descriptions Open
Modern hardware platforms are increasingly complex and heterogeneous. System software uses a hodgepodge of different mechanisms and representations to express the memory topology of the target platform. Considerable maintenance effort is r…
View article: Declarative Power Sequencing
Declarative Power Sequencing Open
Modern computer server systems are increasingly managed at a low level by baseboard management controllers (BMCs). BMCs are processors with access to the most critical parts of the platform, below the level of OS or hypervisor, including c…
View article: mmapx
mmapx Open
Modern Systems-on-Chip (SoCs) are networks of heterogeneous cores, intelligent devices, and memory, connected through multiple configurable address translation and protection units like IOMMUs and System MMUs.
View article: Secure Memory Management on Modern Hardware
Secure Memory Management on Modern Hardware Open
Almost all modern hardware, from phone SoCs to high-end servers with accelerators, contain memory translation and protection hardware like IOMMUs, firewalls, and lookup tables which make it impossible to reason about, and enforce protectio…
View article: Shared Arrangements: practical inter-query sharing for streaming dataflows
Shared Arrangements: practical inter-query sharing for streaming dataflows Open
Current systems for data-parallel, incremental processing and view maintenance over high-rate streams isolate the execution of independent queries. This creates unwanted redundancy and overhead in the presence of concurrent incrementally m…
View article: Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines
Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines Open
This repository contains artifacts of the paper Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines by Reto Achermann, Jayneel Gandhi, Timothy Roscoe, Abhishek Bhattacharjee, and Ashish Panwar to appear in the 25t…
View article: Tackling Hardware/Software co-design from a database perspective
Tackling Hardware/Software co-design from a database perspective Open
Hardware is evolving at a very fast pace due to diverse trends in the IT industry. In the area of data processing, it is fair to say that software often just reacts to these changes, trying to accommodate developments that are not always a…
View article: CleanQ: a lightweight, uniform, formally specified interface for intra-machine data transfer
CleanQ: a lightweight, uniform, formally specified interface for intra-machine data transfer Open
We present CleanQ, a high-performance operating-system interface for descriptor-based data transfer with rigorous formal semantics, based on a simple, formally-verified notion of ownership transfer, with a fast reference implementation. Cl…
View article: Cichlid: Explicit physical memory management for large machines
Cichlid: Explicit physical memory management for large machines Open
In this paper, we rethink how an OS supports virtual memory. Classical VM is an opaque abstraction of RAM, backed by demand paging. However, most systems today (from phones to data-centers) do not page, and indeed may require the performan…
View article: Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory\n Machines
Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory\n Machines Open
Multi-socket machines with 1-100 TBs of physical memory are becoming\nprevalent. Applications running on multi-socket machines suffer non-uniform\nbandwidth and latency when accessing physical memory. Decades of research have\nfocused on d…
View article: A Least-Privilege Memory Protection Model for Modern Hardware
A Least-Privilege Memory Protection Model for Modern Hardware Open
We present a new least-privilege-based model of addressing on which to base memory management functionality in an OS for modern computers like phones or server-based accelerators. Existing software assumptions do not account for heterogene…
View article: Memory-Side Protection With a Capability Enforcement Co-Processor
Memory-Side Protection With a Capability Enforcement Co-Processor Open
Byte-addressable nonvolatile memory (NVM) blends the concepts of storage and memory and can radically improve data-centric applications, from in-memory databases to graph processing. By enabling large-capacity devices to be shared across m…
View article: Shared Arrangements: practical inter-query sharing for streaming\n dataflows
Shared Arrangements: practical inter-query sharing for streaming\n dataflows Open
Current systems for data-parallel, incremental processing and view\nmaintenance over high-rate streams isolate the execution of independent\nqueries. This creates unwanted redundancy and overhead in the presence of\nconcurrent incrementall…
View article: Megaphone: Latency-conscious state migration for distributed streaming dataflows
Megaphone: Latency-conscious state migration for distributed streaming dataflows Open
We design and implement Megaphone, a data migration mechanism for stateful distributed dataflow engines with latency objectives. When compared to existing migration mechanisms, Megaphone has the following differentiating characteristics: (…
View article: Megaphone: Live state migration for distributed streaming dataflows.
Megaphone: Live state migration for distributed streaming dataflows. Open
We design and implement Megaphone, a data migration mechanism for stateful distributed dataflow engines with latency objectives. When compared to existing migration mechanisms, Megaphone has the following differentiating characteristics: (…
View article: DeltaPath: dataflow-based high-performance incremental routing
DeltaPath: dataflow-based high-performance incremental routing Open
Routing controllers must react quickly to failures, reconfigurations and workload or policy changes, to ensure service performance and cost-efficient network operation. We propose a general execution model which views routing as an increme…
View article: SnailTrail: Generalizing Critical Paths for Online Analysis of Distributed Dataflows
SnailTrail: Generalizing Critical Paths for Online Analysis of Distributed Dataflows Open
We rigorously generalize critical path analysis (CPA) to long-running and streaming computations and present SnailTrail, a system built on Timely Dataflow, which applies our analysis to a range of popular distributed dataflow engines. Our …
View article: Formalizing Memory Accesses and Interrupts
Formalizing Memory Accesses and Interrupts Open
The hardware/software boundary in modern heterogeneous multicore computers is increasingly complex, and diverse across different platforms. A single memory access by a core or DMA engine traverses multiple hardware translation and caching …
View article: Explaining outputs in modern data analytics
Explaining outputs in modern data analytics Open
We report on the design and implementation of a general framework for interactively explaining the outputs of modern data-parallel computations, including iterative data analytics. To produce explanations, existing works adopt a naive back…