Tomás Lang
YOU?
Author Swipe
View article: Bound on Run of Zeros and Ones for Images of Floating-Point Numbers by Algebraic Functions
Bound on Run of Zeros and Ones for Images of Floating-Point Numbers by Algebraic Functions Open
This paper presents upper bounds on the number of zeros and ones after the rounding bit for algebraic functions. These functions include reciprocal, division, square root, and inverse square root, which have been considered in previous wor…
View article: Power-delay tradeoffs for radix-4 and radix-8 dividers
Power-delay tradeoffs for radix-4 and radix-8 dividers Open
The use of higher radices in division reduces the n umber of iterations to complete the operation, but increases the complexity of the circuit. In this paper we explore the influence of the radix on the pow er dissipation of a floating-poi…
View article: Exploiting the locality of memory references to reduce the address bus energy
Exploiting the locality of memory references to reduce the address bus energy Open
The energy consumption at the I/O pins is a significant part of the overall chip consumption. This paper presents a method for encoding an external address bus which lowers its activity and, thus, decreases the energy. This method relies o…
View article: Reducing TLB power requirements
Reducing TLB power requirements Open
Article Free Access Share on Reducing TLB power requirements Authors: Toni Juan Depart. of Computer Architecture, Univ. Politècnica de Catalunya, Barcelona (Spain) Depart. of Computer Architecture, Univ. Politècnica de Catalunya, Barcelona…
View article: The difference-bit cache
The difference-bit cache Open
The difference-bit cache is a two-way set-associative cache with an access time that is smaller than that of a conventional one and close or equal to that of a direct-mapped cache. This is achieved by noticing that the two tags for a set h…
View article: The difference-bit cache
The difference-bit cache Open
The difference-bit cache is a two-way set-associative cache with an access time that is smaller than that of a conventional one and close or equal to that of a direct-mapped cache. This is achieved by noticing that the two tags for a set h…
View article: Vector multiprocessors with arbitrated memory access
Vector multiprocessors with arbitrated memory access Open
The high latency of memory accesses is one of the factors that most contribute to reduce the performance of current vector supercomputers. The conflicts that can occur in the memory modules plus the collisions in the interconnection networ…
View article: Increasing the number of strides for conflict-free vector access
Increasing the number of strides for conflict-free vector access Open
Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free vector access for some strides in vector processors with multi-module memories. In this paper, we extend these schemes …
View article: Increasing the number of strides for conflict-free vector access
Increasing the number of strides for conflict-free vector access Open
Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free vector access for some strides in vector processors with multi-module memories. In this paper, we extend these schemes …
View article: Conflict-free access of vectors with power-of-two strides
Conflict-free access of vectors with power-of-two strides Open
An address mapping and an access order is presented for conflict-free access to vectors with any initial address and power-of-two strides. We show that for this conflict-free access it is necessary that the memory be unmatched and present …
View article: CONFLICT-FREE STRIDES FOR VECTORS IN MATCHED MEMORIES
CONFLICT-FREE STRIDES FOR VECTORS IN MATCHED MEMORIES Open
Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access to one family of strides in vector processors with matched memories. In this paper, we extend these schemes to a…
View article: Architectural support for reduced register saving/restoring in single-window register files
Architectural support for reduced register saving/restoring in single-window register files Open
The use of registers in a processor reduces the data and instruction memory traffic. Since this reduction is a significant factor in the improvement of the program execution time, recent VLSI processors have a large number of registers whi…
View article: A reduced register file for RISC architectures
A reduced register file for RISC architectures Open
article Free Access Share on A reduced register file for RISC architectures Authors: Miquel Huguet UCLA Computer Science Department, University of California, Los Angeles, Ca UCLA Computer Science Department, University of California, Los …
View article: A performance evaluation of the multiple bus network for multiprocessor systems
A performance evaluation of the multiple bus network for multiprocessor systems Open
In this paper we present a mathematical model to compute the bandwidth of the multiple bus interconnection network. Due to the computational complexity associated with the exact solution, the processors are removed from the queues at the e…
View article: Database buffer paging in virtual storage systems
Database buffer paging in virtual storage systems Open
Three models, corresponding to different sets of assumptions, are analyzed to study the behavior of a database buffer in a paging environment. The models correspond to practical situations and vary in their search strategies and replacemen…