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A Complementary Survey of Radiation-Induced Soft Error Research: Facilities, Particles, Devices and Trends Open
Soft errors caused by external radiation sources have historically affected the reliability of electronic devices. The radiation effects community has dedicated significant effort to understanding and addressing circuit failures, offering …
Soft Error Assessment of Attitude Estimation Algorithms Running on Resource-Constrained Devices Under Neutron Radiation Open
International audience
Assessment of Radiation-Induced Soft Error on Unmanned Surface Vehicles Open
International audience
Soft Error Assessment of Attitude Estimation Algorithms Running in a Resource-constrained Device under Neutron Radiation Open
This work was partially funded by: MultiRad (PAI project funded by Région Auvergne-Rhône-Alpes); UK EPSRC (EP/R513088/1); IRT Nanoelec (ANR- 10-AIRT-05 project funded by French PIA); UGA/LPSC/GENESIS platform; CAPES; CNPq (grant no. 317087…
Impact of Radiation-Induced Soft Error on Object Detection Algorithm of Unmanned Surface Vehicles Open
This work was partially funded by: MultiRad (PAI project funded by Région Auvergne-Rhône-Alpes); IRT Nanoelec (ANR-10-AIRT-05 project funded by French PIA); UGA/LPSC/GENESIS platform; CAPES; CNPq (317087/2021- 5 and 407477/2022-5); and FAP…
Components to Support Choice in Self-Timed Asynchronous Design Flows Open
The design of digital circuits on recent technologies brings several challenges, among which robustness to variations stands out. Variation sources are multiple, and the evolution of integrated circuit fabrication techniques increases the …
Assessment of Radiation-Induced Soft Errors on Lightweight Cryptography Algorithms Running on a Resource-Constrained Device Open
Most safety-critical edge-computing devices rely on lightweight cryptography (LWC) algorithms to provide security at minimum power and performance overhead. LWC algorithms are traditionally embedded as a hardware component, but with the ad…
Asynchronous Circuit Principles and a Survey of Associated Design Tools Open
Planning and implementing a semiconductor integrated circuit is a highly complex process. Although physical limits seem to be approaching, it currently follows a growing evolutionary path. As deep submicron technologies evolve towards perh…
Robust and Energy-Efficient Hardware: The Case for Asynchronous Design Open
The current technologies behind the design of semiconductor integrated circuits allow embedding billions of components in a singe silicon die, enabling the construction of very complex circuits in a tiny space, dissipating little energy an…
Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison Open
This paper explores asynchronous FIFOs design choices, more specifically FIFOs from the quasi-delay insensitive (QDI) template family. It proposes eight different asynchronous FIFO structures on a CMOS 45nm technology, using a QDI standard…
A differential IR-UWB transmitter using PAM modulation with adaptive PSD Open
The current state of the telecommunications market exhibits a high potential to absorb efficient innovations in wireless connectivity, especially those that can be applied to the Internet of Things and similar domains. Contributing in that…
A GALS Pipeline DES Architecture to Increase Robustness against CPA and CEMA Attacks Open
Side channels attacks (SCAs) are very effective and low cost methods to extract secret information from supposedly secure cryptosystems.The traditional synchronous design flow used to create such systems favors the leakage of information, …
Secure Triple Track Logic Robustness Against Differential Power and Electromagnetic Analyses Open
Side channel attacks (SCA) are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of secure triple track logic (STTL) against power and electromagnetic analyses o…
Buffer Sizing for Multimedia Flows in Packet-Switching NoCs Open
Wormhole packet switching, used in many NoC designs, introduces jitter. This may produce violations of application deadlines. Several works in the literature propose stream workload models, and techniques for buffer sizing. These works do …
A New Router Architecture for High-Performance Intrachip Networks Open
For almost a decade now, Network on Chip (NoC) concepts have evolved to provide an interesting alternative to more traditional intrachip communication architectures (e.g. shared busses) for the design of complex Systems on Chip (SoCs). A c…
Core Communication Interface for FPGAs Open
The use of pre-designed and pre-verified hardware modules, also called IP cores, is an important part of the effort to design and implement complex systems. However, many aspects of IP core manipulation are still to be developed. This pape…
Towards an Integrated Software Development Environment for Robotic Applications in MPSoCs with Support for Energy Estimations Open
Multi-processor Systems-on-Chip (MPSoCs) have been proposed to tackle embedded systems' requirements due to their potential for low-power consumption and high scalability. These systems fit the needs of many application domains, including …
Leveraging QDI Robustness to Simplify the Design of IoT Circuits Open
Internet of Things devices require innovative power efficient design techniques that ensure correct operation in harsh environments, where using synchronous design can be challenging. The timing sign-off of synchronous circuits requires an…
A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow Open
Asynchronous quasi-delay-insensitive circuits are known for their robustness against variations, but their widespread use has been prey to the absence of adequate design methods and lack of design and verification tools. The recently propo…
An IR-UWB pulse generator using PAM modulation with adaptive PSD in 130nm CMOS process Open
This paper proposes an adaptive pulse generator using Pulse Amplitude Modulation (PAM). The circuit was implemented with eight Pulse Generator Units (PGUs) to produce up to eight monocycles per pulse. The number of monocycles per pulse is …
Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations Open
Random number generators find application in many fields, including cryptography, digital signatures and network equipment testers, to cite a few. Two main classes of such generators are usually proposed, pseudo-random number generators an…