Wanshun Zhao
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View article: Surface flattening of 4H-SiC (0001) epitaxial wafers by high temperature oxidation
Surface flattening of 4H-SiC (0001) epitaxial wafers by high temperature oxidation Open
Due to the special ‘step-controlled epitaxy’ mode of 4H-SiC, it is easy to generate step bunching on the surface. Although the flatness of epitaxial wafers has been greatly improved with the advancement of epitaxy technology, there are sti…
View article: Investigation on Step-Bunched Homoepitaxial Layers Grown on On-Axis 4H-SiC Substrates via Molten KOH Etching
Investigation on Step-Bunched Homoepitaxial Layers Grown on On-Axis 4H-SiC Substrates via Molten KOH Etching Open
Wafer-scale on-axis 4H-SiC epitaxial layers with very low roughness were obtained in this study. By performing carbon-rich hydrogen etching and epitaxial growth of the epitaxial layer at different temperatures, local mirror regions (LMRs) …
View article: Surface Uniformity of Wafer-Scale 4H-SiC Epitaxial Layers Grown under Various Epitaxial Conditions
Surface Uniformity of Wafer-Scale 4H-SiC Epitaxial Layers Grown under Various Epitaxial Conditions Open
Wide band gap semiconductor 4H-SiC is currently widely used in the manufacture of high-frequency and high-voltage power devices. The size of commercial 4H-SiC wafers is increasing, from 4 inches to 6 inches. Surface roughness, as one of th…
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Table of Contents Open
View article: Simulation of a Short-Channel 4H-SiC UMOSFET with Buried p Epilayer for Low Oxide Electric Field and Switching Loss
Simulation of a Short-Channel 4H-SiC UMOSFET with Buried p Epilayer for Low Oxide Electric Field and Switching Loss Open
A 4H-SiC UMOSFET structure, which can significantly reduce both the electric field in the gate dielectric and the total switching loss, is characterized by simulation in this letter. The presented structure features a buried p layer (BPL) …