Yaoyu Tao
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View article: Memristive In‐Memory Object Detection with 128 Mb C‐Doped Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> PCM Chip
Memristive In‐Memory Object Detection with 128 Mb C‐Doped Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> PCM Chip Open
Object detection, as a fundamental task in computer vision, mainly performs the classification and localization of objects in images or videos. However, traditional edge computing platforms fall short of meeting the demands for state‐of‐th…
View article: Non-Binary LDPC Arithmetic Error Correction For Processing-in-Memory
Non-Binary LDPC Arithmetic Error Correction For Processing-in-Memory Open
Processing-in-memory (PIM) based on emerging devices such as memristors is more vulnerable to noise than traditional memories, due to the physical non-idealities and complex operations in analog domains. To ensure high reliability, efficie…
View article: Energy‐Efficient Online Training with In Situ Parallel Computing on Electrochemical Memory Arrays
Energy‐Efficient Online Training with In Situ Parallel Computing on Electrochemical Memory Arrays Open
The rapid development of deep learning enables significant breakthroughs for intelligent edge‐terminal devices. However, neural network training for edge computing is currently overly dependent on cloud service platforms, resulting in low …
View article: Fully Hardware Memristive Neuromorphic Computing Enabled by the Integration of Trainable Dendritic Neurons and High‐Density RRAM Chip
Fully Hardware Memristive Neuromorphic Computing Enabled by the Integration of Trainable Dendritic Neurons and High‐Density RRAM Chip Open
Computing‐in‐memory (CIM) architecture inspired by the hierarchy of human brain is proposed to resolve the von Neumann bottleneck and boost acceleration of artificial intelligence. Whereas remarkable progress has been achieved for CIM, mak…
View article: Neural Architecture Search with In‐Memory Multiply–Accumulate and In‐Memory Rank Based on Coating Layer Optimized C‐Doped Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> Phase Change Memory (Adv. Funct. Mater. 15/2024)
Neural Architecture Search with In‐Memory Multiply–Accumulate and In‐Memory Rank Based on Coating Layer Optimized C‐Doped Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> Phase Change Memory (Adv. Funct. Mater. 15/2024) Open
Neural Architecture Search Neural architecture search (NAS) can design neural network models with better performance than manual design. However, the energy and time consumption of conventional software-based NAS are huge, hindering its de…
View article: Seizure detection using dynamic memristor-based reservoir computing and leaky integrate-and-fire neuron for post-processing
Seizure detection using dynamic memristor-based reservoir computing and leaky integrate-and-fire neuron for post-processing Open
Epilepsy is a prevalent neurological disorder, rendering the development of automated seizure detection systems imperative. While complex machine learning models are powerful, their training and hardware deployment remain challenging. The …
View article: Fast and reconfigurable sort-in-memory system enabled by memristors
Fast and reconfigurable sort-in-memory system enabled by memristors Open
Sorting is fundamental and ubiquitous in modern computing systems. Hardware sorting systems are built based on comparison operations with Von Neumann architecture, but their performance are limited by the bandwidth between memory and compa…
View article: Integrated Memristor Network for Physiological Signal Processing
Integrated Memristor Network for Physiological Signal Processing Open
Humans are complex organisms made by millions of physiological systems. Therefore, physiological activities can represent physical or mental states of the human body. Physiological signal processing is essential in monitoring human physiol…
View article: Hadamard product-based in-memory computing design for floating point neural network training
Hadamard product-based in-memory computing design for floating point neural network training Open
Deep neural networks (DNNs) are one of the key fields of machine learning. It requires considerable computational resources for cognitive tasks. As a novel technology to perform computing inside/near memory units, in-memory computing (IMC)…
View article: An Automated FPGA-based Framework for Rapid Prototyping of Nonbinary LDPC Codes
An Automated FPGA-based Framework for Rapid Prototyping of Nonbinary LDPC Codes Open
Nonbinary LDPC codes have shown superior performance close to the Shannon limit. Compared to binary LDPC codes of similar lengths, they can reach orders of magnitudes lower error rate. However, multitude of design freedoms of nonbinary LDP…
View article: HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer
HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer Open
Memory-augmented neural networks (MANNs) provide better inference performance in many tasks with the help of an external memory. The recently developed differentiable neural computer (DNC) is a MANN that has been shown to outperform in rep…
View article: Fast and Scalable Memristive In-Memory Sorting with Column-Skipping Algorithm
Fast and Scalable Memristive In-Memory Sorting with Column-Skipping Algorithm Open
Memristive in-memory sorting has been proposed recently to improve hardware sorting efficiency. Using iterative in-memory min computations, data movements between memory and external processing units can be eliminated for improved latency …
View article: Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes
Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes Open
The error floor phenomenon, associated with iterative decoders, is one of the most significant limitations to the applications of low-density parity-check (LDPC) codes. A variety of techniques from code design to decoder implementation hav…
View article: High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder
High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder Open
Nonbinary polar codes defined over Galois field GF(q) have shown improved error-correction performance than binary polar codes using successive-cancellation list (SCL) decoding. However, nonbinary operations are complex and a direct-mapped…
View article: Algorithm-Architecture Co-Design for Domain-Specific Accelerators in Communication and Artificial Intelligence
Algorithm-Architecture Co-Design for Domain-Specific Accelerators in Communication and Artificial Intelligence Open
The past decade has witnessed an explosive growth of data and the needs for high-speed data communications and processing. The needs continue to drive the development of new hardware for transmitting more data reliably and processing more …
View article: DNC-Aided SCL-Flip Decoding of Polar Codes
DNC-Aided SCL-Flip Decoding of Polar Codes Open
Successive-cancellation list (SCL) decoding of polar codes has been adopted for 5G. However, the performance is not very satisfactory with moderate code length. Heuristic or deep-learning-aided (DL-aided) flip algorithms have been develope…