Yongzheng Zhan
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View article: A 6.6‐GHz Dual‐Path Reference‐Sampling PLL With 139.6‐fs RMS Jitter and −75.2‐dBc Spur in 28‐nm CMOS
A 6.6‐GHz Dual‐Path Reference‐Sampling PLL With 139.6‐fs RMS Jitter and −75.2‐dBc Spur in 28‐nm CMOS Open
This paper presents a dual‐path reference‐sampling phase‐locked loop (RSPLL) with low RMS jitter, low reference spur, and compact area. To suppress the high in‐band phase noise from the G M , an octuple‐sampling phase detector is used to e…
View article: Predicting the Characteristics of High-Speed Serial Links Based on a Deep Neural Network (DNN)—Transformer Cascaded Model
Predicting the Characteristics of High-Speed Serial Links Based on a Deep Neural Network (DNN)—Transformer Cascaded Model Open
The design level of channel physical characteristics has a crucial influence on the transmission quality of high-speed serial links. However, channel design requires a complex simulation and verification process. In this paper, a cascade n…
View article: 41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology
41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology Open
A high-speed, high-depth pre-interleaver in the proposed symbol pre-interleaving Bit MUX (PBM) was implemented to mitigate decision feedback equalizer (DFE) error propagation in a 400 G Ethernet Serializer–Deserializer (SerDes) interface. …
View article: Electrical Transport Properties of Few-Layer SnS2 Field-effect Transistors
Electrical Transport Properties of Few-Layer SnS2 Field-effect Transistors Open
After the discovery of graphene in 2004, two dimensional (2D) materials have fascinated a lot of view due to the excellent properties. Nowadays, the research on 2D materials has spread to other graphene-like layer structured materials, esp…
View article: Low-power 25Gb/s 16:1 Multiplexer for 400Gb/s Ethernet PHY
Low-power 25Gb/s 16:1 Multiplexer for 400Gb/s Ethernet PHY Open
A lower power 25Gb/s 16:1 multiplexer using 65nm CMOS technology for 400Gb/s Ethernet (400GbE) physical layer (PHY) interface was presented. CMOS+CML mixed logic is adopted to achieve hierarchical architecture, avoiding the high clock requ…
View article: DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane
DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane Open
This paper analyzes the effect of error propagation of decision feedback equalizer (DFE) for PAM4 based 400Gb/s Ethernet. First, an analytic model for the error propagation is proposed to estimate the probability of different burst error l…
View article: A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate DFE in 0.13 µm Technology
A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate DFE in 0.13 µm Technology Open
View article: IBIS-AMI Based PAM4 Signaling and FEC Technique for 25 Gb/s Serial Link
IBIS-AMI Based PAM4 Signaling and FEC Technique for 25 Gb/s Serial Link Open