Zhenlin Pei
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View article: System Scenario-Based Design of the Last-Level Cache in Advanced Interconnect-Dominant Technology Nodes
System Scenario-Based Design of the Last-Level Cache in Advanced Interconnect-Dominant Technology Nodes Open
Feature size reduction of the front End of the Line (FEoL) and back End of the Line (BEoL) elements, i.e., transistors and interconnects, has been the main enabler of the next-generation computation systems. The decreasing trend of the cro…
View article: Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus
Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus Open
sponsorship: This work was supported in part by the Inter university Microelectronics Centre (IMEC), in part by the Advanced Scientific Computing Research(ASCR) Program of U.S. Department of Energy (DOE) under Award DE-SC0022881, and in pa…
View article: Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect
Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect Open
status: Published
View article: Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect
Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect Open
sponsorship: This work was partially funded by IMEC, the Department of Energy (DoE) under Award DE-SC0022881, and in part by the National Science Foundation (NSF) under Grant CCF-2219753. (IMEC, Department of Energy (DoE)|DE-SC0022881, Nat…
View article: Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes
Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes Open
Graphene-based interconnects are considered promising replacements for traditional copper (Cu) interconnect due to their great electric properties. In this article, an interconnect-memory co- design framework is developed to efficiently op…