Zunsong Yang
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View article: Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave Detection
Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave Detection Open
View article: A 6.6‐GHz Dual‐Path Reference‐Sampling PLL With 139.6‐fs RMS Jitter and −75.2‐dBc Spur in 28‐nm CMOS
A 6.6‐GHz Dual‐Path Reference‐Sampling PLL With 139.6‐fs RMS Jitter and −75.2‐dBc Spur in 28‐nm CMOS Open
This paper presents a dual‐path reference‐sampling phase‐locked loop (RSPLL) with low RMS jitter, low reference spur, and compact area. To suppress the high in‐band phase noise from the G M , an octuple‐sampling phase detector is used to e…
View article: An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC
An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC Open
This paper proposes an 8-bit synthesizable SAR ADC with inverter-cell-based capacitive digital-to-analog converters (CDACs). An inverter-cell-based capacitor is proposed by connecting the supply and ground ports of the inverter cells toget…
View article: A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering
A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering Open
A phase-locked loop (PLL) employing a split-feedback divider and nested-PLL-based phase-domain low-pass filter (PDLPF) within the harmonic-mixer (HM)-based dual-feedback architecture is presented in this article. The proposed architecture …
View article: Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis
Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis Open
Self-dithered digital delta-sigma modulators (DDSMs) are commonly used in fractional-N frequency synthesizers due to their ability to eliminate unwanted spurs from the synthesizer's spectra without requiring additional hardware. However, w…
View article: A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Open
This paper reports a millimeter (mm)-wave type-II dual-loop phase-locked loop (PLL) with low-power and low-complexity design for improving jitter-power performance and power efficiency. Unlike the typical type-II single-loop PLL using a tr…