Adder
View article: Area efficient approximate multiplier based on novel 4:2 compressors and error correction logic
Area efficient approximate multiplier based on novel 4:2 compressors and error correction logic Open
Multipliers are key components in arithmetic circuits, with their design having a significant impact on overall system performance. Approximate computing techniques seek to improve energy efficiency, processing speed and better use of hard…
View article: Design and Implementation of a 32-bit Pipelined MIPS Processor Using Verilog HDL
Design and Implementation of a 32-bit Pipelined MIPS Processor Using Verilog HDL Open
This work presents the design and implementation of a 32-bit pipelined MIPS processor using Verilog HDL. The processor follows the classical five-stage MIPS architecture consisting of Instruction Fetch (IF), Instruction Decode (ID), Execut…
View article: Design and Implementation of a 32-bit Pipelined MIPS Processor Using Verilog HDL
Design and Implementation of a 32-bit Pipelined MIPS Processor Using Verilog HDL Open
This work presents the design and implementation of a 32-bit pipelined MIPS processor using Verilog HDL. The processor follows the classical five-stage MIPS architecture consisting of Instruction Fetch (IF), Instruction Decode (ID), Execut…
View article: FastLEC: Parallel Datapath Equivalence Checking with Hybrid Engines
FastLEC: Parallel Datapath Equivalence Checking with Hybrid Engines Open
Combinational equivalence checking (CEC) remains a challenge EDA task in the formal verification of datapath circuits due to their complex arithmetic structures and the limited capability or scalability of SAT, BDD, and exact-simulation (E…
View article: FastLEC: Parallel Datapath Equivalence Checking with Hybrid Engines
FastLEC: Parallel Datapath Equivalence Checking with Hybrid Engines Open
Combinational equivalence checking (CEC) remains a challenge EDA task in the formal verification of datapath circuits due to their complex arithmetic structures and the limited capability or scalability of SAT, BDD, and exact-simulation (E…
View article: Accurate Models of NVIDIA Tensor Cores
Accurate Models of NVIDIA Tensor Cores Open
Matrix multiplication is a fundamental operation in for both training of neural networks and inference. To accelerate matrix multiplication, Graphical Processing Units (GPUs) provide it implemented in hardware. Due to the increased through…
View article: Accurate Models of NVIDIA Tensor Cores
Accurate Models of NVIDIA Tensor Cores Open
Matrix multiplication is a fundamental operation in for both training of neural networks and inference. To accelerate matrix multiplication, Graphical Processing Units (GPUs) provide it implemented in hardware. Due to the increased through…
View article: Approximate Multiplier Induced Error Propagation in Deep Neural Networks
Approximate Multiplier Induced Error Propagation in Deep Neural Networks Open
Deep Neural Networks (DNNs) rely heavily on dense arithmetic operations, motivating the use of Approximate Multipliers (AxMs) to reduce energy consumption in hardware accelerators. However, a rigorous mathematical characterization of how A…
View article: Approximate Multiplier Induced Error Propagation in Deep Neural Networks
Approximate Multiplier Induced Error Propagation in Deep Neural Networks Open
Deep Neural Networks (DNNs) rely heavily on dense arithmetic operations, motivating the use of Approximate Multipliers (AxMs) to reduce energy consumption in hardware accelerators. However, a rigorous mathematical characterization of how A…
View article: Hardware Software Optimizations for Fast Model Recovery on Reconfigurable Architectures
Hardware Software Optimizations for Fast Model Recovery on Reconfigurable Architectures Open
Model Recovery (MR) is a core primitive for physical AI and real-time digital twins, but GPUs often execute MR inefficiently due to iterative dependencies, kernel-launch overheads, underutilized memory bandwidth, and high data-movement lat…
View article: Hardware Software Optimizations for Fast Model Recovery on Reconfigurable Architectures
Hardware Software Optimizations for Fast Model Recovery on Reconfigurable Architectures Open
Model Recovery (MR) is a core primitive for physical AI and real-time digital twins, but GPUs often execute MR inefficiently due to iterative dependencies, kernel-launch overheads, underutilized memory bandwidth, and high data-movement lat…
View article: Senary Hypercubic Computational Logic Architecture: A Full Academic Suite with Verilog HDL
Senary Hypercubic Computational Logic Architecture: A Full Academic Suite with Verilog HDL Open
This record presents the complete Senary Electron Paradigm and its implementation. The submission includes the core theoretical paper, a comprehensive Verilog HDL Blueprints Suite for the Sixtinary CPU (including arithmetic, token routing,…
View article: Senary Hypercubic Computational Logic Architecture: A Full Academic Suite with Verilog HDL
Senary Hypercubic Computational Logic Architecture: A Full Academic Suite with Verilog HDL Open
This record presents the complete Senary Electron Paradigm and its implementation. The submission includes the core theoretical paper, a comprehensive Verilog HDL Blueprints Suite for the Sixtinary CPU (including arithmetic, token routing,…
View article: The Residual Computer:A Universal Residual Architecture Based on Analytic Structure
The Residual Computer:A Universal Residual Architecture Based on Analytic Structure Open
We demonstrate the first universal digital computer that requires no physical hardware. Arbitrary bitstrings are encoded as localized phase pulses in the critical-line trajectory of an analytic function. The resulting residual deviation fi…
View article: Continuous and M-ary Phase Logic in π-Layer Geometry Computing: A Cryogenic All-Dielectric Extension for High-Density Reversible Computation
Continuous and M-ary Phase Logic in π-Layer Geometry Computing: A Cryogenic All-Dielectric Extension for High-Density Reversible Computation Open
This paper presents a comprehensive extension of the π-Layer Geometry Computing (π-GC) paradigm — a fully dielectric, cryogenic, and reversible logic platform where information is encoded in the geometric phase (Φ) of confined photons rath…
View article: Continuous and M-ary Phase Logic in π-Layer Geometry Computing: A Cryogenic All-Dielectric Extension for High-Density Reversible Computation
Continuous and M-ary Phase Logic in π-Layer Geometry Computing: A Cryogenic All-Dielectric Extension for High-Density Reversible Computation Open
This paper presents a comprehensive extension of the π-Layer Geometry Computing (π-GC) paradigm — a fully dielectric, cryogenic, and reversible logic platform where information is encoded in the geometric phase (Φ) of confined photons rath…
View article: The Modular Spectrum of π: Theoretical Unification, DSP Isomorphism, and Exascale Validation
The Modular Spectrum of π: Theoretical Unification, DSP Isomorphism, and Exascale Validation Open
This repository presents the definitive consolidation of the "Modular Spectrum" theoretical framework, which resolves the discontinuity between the discrete nature of integers and the transcendental periodicity of trigonometric functions t…
View article: The Modular Spectrum of π: Theoretical Unification, DSP Isomorphism, and Exascale Validation
The Modular Spectrum of π: Theoretical Unification, DSP Isomorphism, and Exascale Validation Open
This repository presents the definitive consolidation of the "Modular Spectrum" theoretical framework, which resolves the discontinuity between the discrete nature of integers and the transcendental periodicity of trigonometric functions t…
View article: Entropica: 1024-mode unitary evolution with Born-rule readout, trained on TinyStories in under 2 hours on a laptop GPU
Entropica: 1024-mode unitary evolution with Born-rule readout, trained on TinyStories in under 2 hours on a laptop GPU Open
Entropica is the first generative language model whose forward pass is physically realizable as a passive linear-optical interferometer (zero electrical power during inference). A 1024-mode, 32-layer unitary network using only Reck-scheme …
View article: Entropica: 1024-mode unitary evolution with Born-rule readout, trained on TinyStories in under 2 hours on a laptop GPU
Entropica: 1024-mode unitary evolution with Born-rule readout, trained on TinyStories in under 2 hours on a laptop GPU Open
Entropica is the first generative language model whose forward pass is physically realizable as a passive linear-optical interferometer (zero electrical power during inference). A 1024-mode, 32-layer unitary network using only Reck-scheme …
View article: Area and Power Optimized 8×8 Truncated and 8×8 Array Multiplier Using Hybrid 1 Bit Full Adders
Area and Power Optimized 8×8 Truncated and 8×8 Array Multiplier Using Hybrid 1 Bit Full Adders Open
Multiplication is a fundamental operation in digital signal processing (DSP), neural network accelerators, and embedded systems. Conventional parallel multipliers offer high performance but incur considerable area and power overhead, espec…
View article: Area and Power Optimized 8×8 Truncated and 8×8 Array Multiplier Using Hybrid 1 Bit Full Adders
Area and Power Optimized 8×8 Truncated and 8×8 Array Multiplier Using Hybrid 1 Bit Full Adders Open
Multiplication is a fundamental operation in digital signal processing (DSP), neural network accelerators, and embedded systems. Conventional parallel multipliers offer high performance but incur considerable area and power overhead, espec…
View article: Kernelized Decoded Quantum Interferometry
Kernelized Decoded Quantum Interferometry Open
Decoded Quantum Interferometry (DQI) promises superpolynomial speedups for structured optimization; however, its practical realization is often hindered by significant sensitivity to hardware noise and spectral dispersion. To bridge this g…
View article: Kernelized Decoded Quantum Interferometry
Kernelized Decoded Quantum Interferometry Open
Decoded Quantum Interferometry (DQI) promises superpolynomial speedups for structured optimization; however, its practical realization is often hindered by significant sensitivity to hardware noise and spectral dispersion. To bridge this g…
View article: Transistor‐Level Activation Functions via Two‐Gate Designs: From Analog Sigmoid and Gaussian Control to Real‐Time Hardware Demonstrations
Transistor‐Level Activation Functions via Two‐Gate Designs: From Analog Sigmoid and Gaussian Control to Real‐Time Hardware Demonstrations Open
Tunable analog activation functions are essential for energy‐efficient artificial intelligence (AI) hardware. Two transistor designs are presented: the sigmoid‐like activation function transistor (SA‐transistor) and the Gaussian‐like activ…
View article: Vertical Self‐Rectifying Memristive Arrays for Page‐Wise Parallel Logic and Arithmetic Processing
Vertical Self‐Rectifying Memristive Arrays for Page‐Wise Parallel Logic and Arithmetic Processing Open
Logic‐in‐memory (LIM) architectures are explored to address the data transfer bottleneck of conventional von Neumann architectures by integrating computation directly within memory arrays. Among various candidates, memristor‐based LIM syst…
View article: Design of High-Speed 8-Bit Vedic Multiplier Using Brent-Kung Parallel Prefix Adder
Design of High-Speed 8-Bit Vedic Multiplier Using Brent-Kung Parallel Prefix Adder Open
One of the primary purposes of a digital signal processing system is multiplication. The multiplier’s performance affects the DSP system’s overall performance. Therefore, it is crucial to create an effective and quick multiplier implementa…
View article: Design of High-Speed 8-Bit Vedic Multiplier Using Brent-Kung Parallel Prefix Adder
Design of High-Speed 8-Bit Vedic Multiplier Using Brent-Kung Parallel Prefix Adder Open
One of the primary purposes of a digital signal processing system is multiplication. The multiplier’s performance affects the DSP system’s overall performance. Therefore, it is crucial to create an effective and quick multiplier implementa…
View article: Error-Resilient Hardware Design with Approximate Computing: A Review of Circuit-Level and System-Level Optimization Strategies
Error-Resilient Hardware Design with Approximate Computing: A Review of Circuit-Level and System-Level Optimization Strategies Open
Approximate computing (AxC) is a method that allows tiny and controlled errors in exchange for lower power consumption and reduced hardware cost. It offers an effective way to balance computational accuracy and efficiency in error-tolerant…
View article: Design of low-power, high-speed approximate 4:2 compressors for efficient partial product reduction in multipliers
Design of low-power, high-speed approximate 4:2 compressors for efficient partial product reduction in multipliers Open
Partial product reduction becomes the main task in the multiplication process. Therefore, the partial product stages of multipliers are reduced with the usage of compressors, by using compressors in the multiplier. Using compressors in the…