Delay calculation
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Compact Cascadable g m -C All-Pass True Time Delay Cell With Reduced Delay Variation Over Frequency Open
At low-GHz frequencies, analog time-delay cells realized by LC delay lines or transmission lines are unpractical in CMOS, due to their large size. As an alternative, delays can be approximated by all-pass filters exploiting transconductors…
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Role of delay-times in delay-based photonic reservoir computing [Invited] Open
Delay-based reservoir computing has gained a lot of attention due to the relative simplicity with which this concept can be implemented in hardware. However, unnecessary constraints are commonly placed on the relationship between the delay…
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Exposing End-to-End Delay in Software-Defined Networking Open
Software-Defined Networking (SDN) shows us a promising picture to deploy the demanding services in a fast and cost-effective way. Till now, most SDN use cases are deployed in enterprise/campus networks and data center networks. However, wh…
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Calculating Accurate End-to-End Delay Bounds - You Better Know Your Cross-Traffic Open
Bounds on the end-to-end delay of data flows play a crucial role in different areas, ranging from certification of hard real-time communication capabilities to quality of experience assurance for end users. Deterministic Network Calculus (…
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An Accurate Method for Delay Margin Computation for Power System Stability Open
The application of the phasor measurement units and the wide expansion of the wide area measurement units make the time delay inevitable in power systems. The time delay could result in poor system performance or at worst lead to system in…
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Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration Open
This paper presents a time-to-digital converter (TDC) based on a field programmable gate array (FPGA) with a tapped delay line (TDL) architecture. This converter employs dual delay lines (DDLs) to enable real-time calibrations, and the pro…
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A high-resolution programmable Vernier delay generator based on carry chains in FPGA Open
This paper presents an architecture of a high-resolution delay generator implemented in a single field programmable gate array chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various ph…
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Enabling exact delay synthesis Open
Given (i) a Boolean function, (ii) a set of arrival times at the inputs, and (iii) a gate library with associated delay values, the exact delay synthesis problem asks for a circuit implementation which minimizes the arrival time at the out…
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Design impacts of delay invariant high‐speed clock delayed dual keeper domino circuit Open
Precise keeper control of domino logic circuit can significantly increase the speed of operation. However, the positive feedback gain associated with the feedback keeper circuit unduly increases the delay variability. Here, a novel high‐sp…
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Time‐based all‐digital time‐to‐digital converter with pre‐skewed bi‐directional gated delay line time integrator Open
An all‐digital first‐order single‐bit time‐to‐digital converter (TDC) with a pre‐skewed bi‐directional gated delay line (PS‐BDGDL) time integrator with built‐in self‐quantisation is presented in this study. Pre‐skewing is utilised to lower…
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Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model Open
Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes' toggle rate. This paper discusses a deterministic and…
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One-Way Active Delay Measurement With Error Bounds Open
This paper deals with the problem of measuring the delay of a packet in a network with an associated error bound, but without having a need for clock synchronization and for any form of bidirectional messaging between the sender and receiv…
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Continuously tunable silicon optical true-time delay lines with a large delay tuning range and a low delay fluctuation Open
On-chip switchable optical true-time delay lines (OTTDLs) feature a large group delay tuning range but suffer from a discrete tuning step. OTTDLs with a large delay tuning range and a continuous tuning capability are highly desired. In thi…
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Two-Stage Clock-Free Time-to-Digital Converter Based on Vernier and Tapped Delay Lines in FPGA Device Open
This article presents an idea, design and test results of a new time-to-digital converter (TDC) implemented in an FPGA device. The high resolution of 13 ps and measurement range of 3.4 ns are achieved based on a two-stage time interpolatio…
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Total-delay-based Max Pressure: A Max Pressure Algorithm Considering Delay Equity Open
This paper proposes a novel decentralized signal control algorithm that seeks to improve traffic delay equity, measured as the variation of delay experienced by individual vehicles. The proposed method extends the recently developed delay-…
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Artificial neural network model for arrival time computation in gate level circuits Open
Advances in the VLSI process technology lead to variations in the process parameters. These process variations severely affect the delay computation of a digital circuit. Under such variations, the various delays, i.e. net delay, gate dela…
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Stability Analysis of Time-Delay Systems via a Delay-Derivative-Partitioning Approach Open
This paper is devoted to the study of delay-dependent stability of time-varying delay systems. A delay-derivative-partitioning approach is proposed. By constructing an augmented Lyapunov functional that contains two delay-product-dependent…
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Timing-driven placement algorithm based on delay matrix model for reconfigurable system-on-chip Open
Placement is one of the most difficult stages of reconfigurable system-on-chip design flow.Designing highspeed systems requires efficient timing-driven placement algorithms.In this article we present a new timing-driven placement algorithm…
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A 0.2–2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55–448.6 ns Programmable Delay Range and 330 ns/mm<sup>2</sup> Area Efficiency Open
Simulation of radar returns, full-duplex systems, and signal repeaters require hundreds of ns of programmable broadband radio frequency (RF) delay in the signal path to simulate large distances in the case of radar returns, for signal canc…
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Optimized routing protocol for broadband hybrid satellite constellation communication IP network system Open
Long delays and varying delays in triple-play services on a hybrid satellite network are constraints lead for quality of service in end-to-end delay; it is an origin of jitter to make obstacle such as motion freezes and block artifacts in …
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Design and analysis of High-Speed Low-Power Vedic Multiplier with 3-1-1-2 compressor Using Reversible Logic gates Open
The FFT Function in digital signal processing is one of the most important function in several applications such as Image Processing, Wireless Communications and Multimedia. FFT Processors consisting of butterfly structure operations invol…
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Stochastic Delay Cost Functions to Estimate Delay Propagation Under Uncertainty Open
We provide a mathematical formulation of flight-specific delay cost functions that enables a detailed tactical consideration of how a given flight delay will interact with all downstream constraints in the respective aircraft rotation. The…
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Interconnected delay and state observer for nonlinear systems with time-varying input delay Open
This work presents a general framework to estimate both state and delay thanks to two interconnected observers. This scheme can be applied to a large class of nonlinear systems with time-varying input delay. In order to illustrate this app…
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An Improved Path Delay Variability Model via Multi-Level Fan-Out-of-4 Metric for Wide-Voltage-Range Digital CMOS Circuits Open
In advanced CMOS technology, process, voltage, and temperature (PVT) variations increase the paths' latency in digital circuits, especially when operating at a low supply voltage. The fan-out-of-4 inverter chain (FO4 chain) metric has been…
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A Computationally Efficient Model for FDSOI MOSFETs and Its Application for Delay Variability Analysis Open
This paper proposes a compact, physics-based current model for fully depleted silicon-on-insulator (FDSOI) MOSFETs and applies it to delay variability analysis. An analytical method is applied to avoid the numerical iterations required in …
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Cross-Corner Delay Variation Model for Standard Cell Libraries Open
For timing closure of logic circuits, circuit designers must perform sign-offs on a variety of process, voltage, and temperature (PVT) conditions. Designs of advanced logic circuits involve a multitude of voltage islands and operating mode…
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TDC with uncontrolled delay lines: calibration approaches and precision improvement methods Open
The time-to-digital-converter (TDC) using uncontrolled delay lines has a simple structure and finer measurement precision since the delay cells are pure digital gates that operate at maximum speed. For every incoming hit, two “snapshots” o…
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Data-driven room acoustic modeling via differentiable feedback delay networks with learnable delay lines Open
Over the past few decades, extensive research has been devoted to the design of artificial reverberation algorithms aimed at emulating the room acoustics of physical environments. Despite significant advancements, automatic parameter tunin…
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Machine-Learning Based Delay Prediction for FPGA Technology Mapping Open
Accurate delay prediction is important in the early stages of logic and high-level synthesis. In technology mapping for field programmable gate array (FPGA), a gate-level circuit is transcribed into a lookup table (LUT)-level circuit. Quic…
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An Effective Method for Interconnect Delay Optimization of ASIC’s Open
With the development of integrated circuit design into 65nm process, interconnect delay has become one of the key factors that hinder the convergence of time sequence. Firstly, the determinants of interconnect delay are analyzed by Elmore …