Physical address
View article: Translation leak-aside buffer : Defeating cache side-channel protections with TLB attacks
Translation leak-aside buffer : Defeating cache side-channel protections with TLB attacks Open
To stop side channel attacks on CPU caches that have allowed attackers to leak secret information and break basic security mechanisms, the security community has developed a variety of powerful defenses that effectively isolate the securit…
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Large pages and lightweight memory management in virtualized environments Open
Large pages have long been used to mitigate address translation overheads on big-memory systems, particularly in virtualized environments where TLB miss overheads are severe. We show, however, that far from being a panacea, large pages are…
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NumaGiC Open
On contemporary cache-coherent Non-Uniform Memory Access (ccNUMA) architectures, applications with a large memory footprint suffer from the cost of the garbage collector (GC), because, as the GC scans the reference graph, it makes many rem…
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Prefetched Address Translation Open
With explosive growth in dataset sizes and increasing machine memory capacities, per-application memory footprints are commonly reaching into hundreds of GBs. Such huge datasets pressure the TLB, resulting in frequent misses that must be r…
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Panthera: holistic memory management for big data processing over hybrid memories Open
Modern data-parallel systems such as Spark rely increasingly on in-memory computing that can significantly improve the efficiency of iterative algorithms. To process real-world datasets, modern data-parallel systems often require extremely…
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Translation ranger Open
Virtual memory (VM) eases programming effort but can suffer from high address translation overheads. Architects have traditionally coped by increasing Translation Lookaside Buffer (TLB) capacity; this approach, however, requires considerab…
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Umpire: Application-focused management and coordination of complex hierarchical memory Open
Advanced architectures like Sierra provide a wide range of memory resources that must often be carefully controlled by the user. These resources have varying capacities, access timing rules, and visibility to different compute resources. A…
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The XGBoost Approach Tuned by TLB Metaheuristics for Fraud Detection Open
The recent pandemic had a major impact on online transactions.With this trend, credit card fraud increased.For the solution to this problem the authors explore existing solutions and propose an optimized solution.The solution is based on a…
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Disaggregated Cloud Memory with Elastic Block Management Open
With the growing importance of in-memory data processing, cloud service providers have launched large memory virtual machine services to accommodate memory intensive workloads. Such large memory services using low volume scaled-up machines…
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Near-Memory Address Translation Open
Virtual memory (VM) is a crucial abstraction in modern computer systems at any scale, from handheld devices to datacenters. VM provides programmers the illusion of an always sufficiently large and linear memory, making programming easier. …
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Supporting Superpages and Lightweight Page Migration in Hybrid Memory Systems Open
Superpages have long been used to mitigate address translation overhead in large-memory systems. However, superpages often preclude lightweight page migration, which is crucial for performance and energy efficiency in hybrid memory systems…
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Compiler assisted hybrid implicit and explicit GPU memory management under unified address space Open
To improve programmability and productivity, recent GPUs adopt a virtual memory address space shared with CPUs (e.g., NVIDIA's unified memory). Unified memory migrates the data management burden from programmers to system software and hard…
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Exploiting Page Table Locality for Agile TLB Prefetching Open
Frequent Translation Lookaside Buffer (TLB) misses incur high performance and energy costs due to page walks required for fetching the corresponding address translations. Prefetching page table entries (PTEs) ahead of demand TLB accesses c…
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A Survey of Resource Management for Processing-In-Memory and Near-Memory Processing Architectures Open
Due to the amount of data involved in emerging deep learning and big data applications, operations related to data movement have quickly become a bottleneck. Data-centric computing (DCC), as enabled by processing-in-memory (PIM) and near-m…
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Secure TLBs Open
This paper focuses on a new attack vector in modern processors: the timing-based side and covert channel attacks due to the Translation Look-aside Buffers (TLBs). This paper first presents a novel three-step modeling approach that is used …
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Larger-than-memory data management on modern storage hardware for in-memory OLTP database systems Open
In-memory database management systems (DBMSs) outperform disk-oriented systems for on-line transaction processing (OLTP) workloads. But this improved performance is only achievable when the database is smaller than the amount of physical m…
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NumaMMA Open
International audience
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Big data causing big (TLB) problems Open
GPUs are increasingly adopted for large-scale database processing, where data accesses represent the major part of the computation. If the data accesses are irregular, like hash table accesses or random sampling, the GPU performance can su…
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Rebooting Virtual Memory with Midgard Open
Virtual Memory (VM) is a critical programming abstraction that is widely used in various modern computing platforms. With the rise of datacenter computing and birth of planet-scale online services, the semantic and capacity requirements fr…
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Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors Open
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MASK Open
Graphics Processing Units (GPUs) exploit large amounts of threadlevel parallelism to provide high instruction throughput and to efficiently hide long-latency stalls. The resulting high throughput, along with continued programmability impro…
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A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels Open
Ever-increasing demands for main memory bandwidth and memory speed/power tradeoff led to the introduction of memories with multiple memory channels, such as Wide IO DRAM. Efficient utilization of a multichannel memory as a shared resource …
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Survey on memory management techniques in heterogeneous computing systems Open
A major issue faced by data scientists today is how to scale up their processing infrastructure to meet the challenge of big data and high‐performance computing (HPC) workloads. With today's HPC domain, it is required to connect multiple g…
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Contiguitas: The Pursuit of Physical Memory Contiguity in Datacenters Open
The unabating growth of the memory needs of emerging datacenter applications has exacerbated the scalability bottleneck of virtual memory. However, reducing the excessive overhead of address translation will remain onerous until the physic…
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Hardware-Assisted Thread and Data Mapping in Hierarchical Multicore Architectures Open
The performance and energy efficiency of modern architectures depend on memory locality, which can be improved by thread and data mappings considering the memory access behavior of parallel applications. In this article, we propose intense…
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MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memory Open
In recent years, we are witnessing a trend toward in-memory computing for future generations of computers that differs from traditional von-Neumann architecture in which there is a clear distinction between computing and memory units. Cons…
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T unne L s for B ootlegging: Fully Reverse-Engineering GPU TLBs for Challenging Isolation Guarantees of NVIDIA MIG Open
Recent studies have revealed much detailed information about the translation lookaside buffers (TLBs) of modern CPUs, but we find that many properties of such components in modern GPUs still remain unknown or unclear. To fill this knowledg…
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Using TLB Speculation to Overcome Page Splintering in Virtual Machines Open
As systems provide increasing memory capacities to support memory-intensive workloads, Translation Lookaside Buffers (TLBs) are becoming a critical performance bottleneck. TLB performance is exacerbated with virtualization, which is typica…
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PTEMagnet: fine-grained physical memory reservation for faster page walks in public clouds Open
The last few years have seen a rapid adoption of cloud computing for data-intensive tasks. In the cloud environment, it is common for applications to run under virtualization and to share a virtual machine with other applications (e.g., in…
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Adaptive huge-page subrelease for non-moving memory allocators in warehouse-scale computers Open
Modern C++ server workloads rely on 2 MB huge pages to improve memory system performance via higher TLB hit rates. Huge pages have traditionally been supported at the kernel level, but recent work has shown that user-level, huge page-aware…