Clock signal
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Tight real-time synchronization of a microwave clock to an optical clock across a turbulent air path Open
The ability to distribute the precise time and frequency from an optical clock to remote platforms could enable future precise navigation and sensing systems. Here we demonstrate tight, real-time synchronization of a remote microwave clock…
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Time-to-Digital Converter IP-Core for FPGA at State of the Art Open
The Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time-Mode (TM) circuits almost unfeasible. In particular, in Programmable Logic (PL) devices…
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The Drosophila Clock Neuron Network Features Diverse Coupling Modes and Requires Network-wide Coherence for Robust Circadian Rhythms Open
In animals, networks of clock neurons containing molecular clocks orchestrate daily rhythms in physiology and behavior. However, how various types of clock neurons communicate and coordinate with one another to produce coherent circadian r…
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Precise Clock Synchronization in High Performance Wireless Communication for Time Sensitive Networking Open
In this paper, an enhanced precision time protocol (PTP) to enable precise clock synchronization between the nodes within an industrial wireless sensor network deployed for critical control and automation applications is proposed. As it wi…
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A Novel Quartz Clock With Integrated Wireless Energy Harvesting and Sensing Functions Open
There has been an increasing demand for smart devices and smart furniture for home automation, monitoring, and security applications. In this paper, we present a novel method of integrating the function of wireless energy harvesting from a…
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Decawave UWB Clock Drift Correction and Power Self-Calibration Open
The position accuracy based on Decawave Ultra-Wideband (UWB) is affected mainly by three factors: hardware delays, clock drift, and signal power. This article discusses the last two factors. The general approach to clock drift correction u…
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An extra-clock ultradian brain oscillator sustains circadian timekeeping Open
The master circadian clock generates 24-hour rhythms to orchestrate daily behavior, even running freely under constant conditions. Traditionally, the master clock is considered self-sufficient in sustaining free-running timekeeping via its…
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Rail-to-Rail Timing Signals Generation Using InGaZnO TFTs For Flexible X-Ray Detector Open
This paper reports on-chip rail-to-rail timing signals generation thin-film circuits for the first time. These circuits, based on a-IGZO thin-film transistors (TFTs) with a simple staggered bottom gate structure, allow row and column selec…
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Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops Open
Optimization for power is one of the most important design objectives in modern digital signal processing (DSP) applications. The digital finite duration impulse response (FIR) filter is considered to be one of the most essential component…
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Designing approximate circuits using clock overgating Open
Approximate computing is an emerging paradigm to improve the efficiency of computing systems by leveraging the intrinsic resilience of applications to their computations being executed in an approximate manner. Prior efforts on approximate…
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A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs Open
The upcoming 100 Gb/s links in the next-generation ethernet passive optical networks will be based on four channels of 25 Gb/s. The corresponding transceivers in these optical links require a high-speed clock and data recovery circuit to e…
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Asynchronous ballistic reversible computing Open
Most existing concepts for hardware implementation of reversible computing invoke an adiabatic computing paradigm, in which individual degrees of freedom (e.g., node voltages) are synchronously transformed under the influence of externally…
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Optical-lattice-based Cs active clock with a continual superradiant lasing signal Open
We demonstrate state-of-the-art technique of an active clock to provide a\ncontinuous superradiant lasing signal using an ensemble of trapped Cs atoms in\nthe optical lattice. A magic wavelength of the proposed |7S1/2; F = 4, MF = 0>\n- |6…
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8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment Open
Digital PLLs are popular for on-chip clock generation due to their small size and technology portability. Variability tolerance is a key design challenge when designing such PLLs in an advanced CMOS technology. Environmental variations, su…
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A Design Flow for Click-Based Asynchronous Circuits Design With Conventional EDA Tools Open
The "event-driven" feature of asynchronous circuits enables the circuits to work when and where needed, making it a good alternative to design low-power circuits. However, asynchronous circuits are not widely adopted as a consequence of th…
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Joint clock recovery and feed-forward equalization for PAM4 transmission Open
With the rapid development of cloud services, data-center applications and the Internet of Things, short-reach communications have attracted much more attention in recent years. 4-level pulse amplitude modulation (PAM4) is a promising modu…
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Multiplication-free timing phase error detector for Nyquist and non-Nyquist optical signals Open
A versatile digital coherent receiver capable of handling optical signals with different kinds of pulse shaping schemes (PSSs) is indispensable for future flexible and heterogeneous coherent optical communication networks. Therefore, a low…
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Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS Open
This article demonstrates a digitally friendly time-based analog-to-digital converter (ADC) exploiting Dickson charge-pump (CP) as part of a voltage-to-time conversion (VTC) implemented in 28-nm CMOS. In the proposed technique, the Dickson…
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A Smart Sensor for Defending against Clock Glitching Attacks on the I2C Protocol in Robotic Applications Open
This paper presents a study about hardware attacking and clock signal vulnerability. It considers a particular type of attack on the clock signal in the I2C protocol, and proposes the design of a new sensor for detecting and defending agai…
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DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment Open
This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on t…
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Design and Implementation of Power-Efficient FSM based UART Open
The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication pro…
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From Multiphase to Novel Single-Phase Multichannel Shift-Clock Fast Counter Time-to-Digital Converter Open
With countless applications, time measurements are among industrial electronics' current most important challenges. This is not a matter of precision, which by now standard architectures have brought in the order of picoseconds and therefo…
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A Software-based Low-Jitter Servo Clock for Inexpensive Phasor Measurement Units Open
This paper presents the design and the implementation of a servo-clock (SC) for low-cost Phasor Measurement Units (PMUs). The SC relies on a classic Proportional Integral (PI) controller, which has been properly tuned to minimize the synch…
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Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA Open
The authors present a new method for the generation of pseudorandom bits, based on coupled variable input linear congruential generator (LCG) and a clock divider. To prevent the system from falling into short‐period orbits as well as incre…
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A Fast Transient Response Digital LDO with a TDC-Based Signal Converter Open
The digital low drop-out regulator (LDO) has been used widely in digital circuits for its low supply voltage characteristics. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the…
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Asynchronous Floating-Point Adders and Communication Protocols: A Survey Open
Addition is the key operation in digital systems, and floating-point adder (FPA) is frequently used for real number addition because floating-point representation provides a large dynamic range. Most of the existing FPA designs are synchro…
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An Asynchronous Pipelined Time-to-Digital Converter Using Time-Domain Subtraction Open
This paper presents the design of a low-power asynchronous pipelined time-to-digital converter (AP-TDC) to be employed in a time-domain signal processing system. The presented AP-TDC utilizes two novel concepts, namely time-domain subtract…
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Real-time FPGA prototyping of a 15GBaud SP-16QAM coherent optical receiver with optimal interpolating for clock recovery and equalization Open
We demonstrate a real-time coherent optical receiver based on a single field programmable gate array (FPGA) chip. To strike the balance between the performance and hardware resources, we use a clock recovery scheme using the optimal interp…
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FPGA and ASIC realisation of EMD algorithm for real‐time signal processing Open
In this study, the authors have proposed both field‐programmable gate array (FPGA) and application specific integrated circuit (ASIC) based realisation of the empirical mode decomposition (EMD) algorithm for the real‐time signal processing…
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Two-Stage Clock-Free Time-to-Digital Converter Based on Vernier and Tapped Delay Lines in FPGA Device Open
This article presents an idea, design and test results of a new time-to-digital converter (TDC) implemented in an FPGA device. The high resolution of 13 ps and measurement range of 3.4 ns are achieved based on a two-stage time interpolatio…