Digital clock manager
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A Compact Model for the Complex Plant Circadian Clock Open
The circadian clock is an endogenous timekeeper that allows organisms to anticipate and adapt to the daily variations of their environment. The plant clock is an intricate network of interlocked feedback loops, in which transcription facto…
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A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers Open
True random number generators (TRNGs) are fundamentals in many important security applications. Though they exploit randomness sources that are typical of the analog domain, digital-based solutions are strongly required especially when the…
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Precise Clock Synchronization in High Performance Wireless Communication for Time Sensitive Networking Open
In this paper, an enhanced precision time protocol (PTP) to enable precise clock synchronization between the nodes within an industrial wireless sensor network deployed for critical control and automation applications is proposed. As it wi…
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A Novel Quartz Clock With Integrated Wireless Energy Harvesting and Sensing Functions Open
There has been an increasing demand for smart devices and smart furniture for home automation, monitoring, and security applications. In this paper, we present a novel method of integrating the function of wireless energy harvesting from a…
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Decawave UWB Clock Drift Correction and Power Self-Calibration Open
The position accuracy based on Decawave Ultra-Wideband (UWB) is affected mainly by three factors: hardware delays, clock drift, and signal power. This article discusses the last two factors. The general approach to clock drift correction u…
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Novel Maximum Likelihood Estimation of Clock Skew in One-Way Broadcast Time Synchronization Open
Clock skew compensation is essential for accurate time synchronization in\nwireless networks. However, contemporary clock skew estimation is based on\ninaccurate transmission time measurement, which makes credible estimation\nchallenging. …
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A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs Open
The upcoming 100 Gb/s links in the next-generation ethernet passive optical networks will be based on four channels of 25 Gb/s. The corresponding transceivers in these optical links require a high-speed clock and data recovery circuit to e…
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Clock Synchronization in Virtualized Distributed Real-Time Systems Using IEEE 802.1AS and ACRN Open
Virtualization of distributed real-time systems enables the consolidation of mixed-criticality functions on a shared hardware platform, easing system integration. Time-triggered communication and computation can act as an enabler of safe h…
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An Improved Network Time Protocol for Industrial Internet of Things Open
In the industrial Internet of Things, the network time protocol (NTP) can be used for time synchronization, allowing machines to run in sync so that machines can take critical actions within 1 ms. However, the commonly used NTP mechanism d…
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DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment Open
This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on t…
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Design and Implementation of Power-Efficient FSM based UART Open
The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication pro…
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A System for Clock Synchronization in an Internet of Things Open
Synchronizing clocks on Internet of Things (IoT) devices is important for applications such as monitoring and real time control. In this paper, we describe a system for clock synchronization in IoT devices that is designed to be scalable, …
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A Software-based Low-Jitter Servo Clock for Inexpensive Phasor Measurement Units Open
This paper presents the design and the implementation of a servo-clock (SC) for low-cost Phasor Measurement Units (PMUs). The SC relies on a classic Proportional Integral (PI) controller, which has been properly tuned to minimize the synch…
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Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA Open
The authors present a new method for the generation of pseudorandom bits, based on coupled variable input linear congruential generator (LCG) and a clock divider. To prevent the system from falling into short‐period orbits as well as incre…
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Asynchronous Floating-Point Adders and Communication Protocols: A Survey Open
Addition is the key operation in digital systems, and floating-point adder (FPA) is frequently used for real number addition because floating-point representation provides a large dynamic range. Most of the existing FPA designs are synchro…
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Two-Stage Clock-Free Time-to-Digital Converter Based on Vernier and Tapped Delay Lines in FPGA Device Open
This article presents an idea, design and test results of a new time-to-digital converter (TDC) implemented in an FPGA device. The high resolution of 13 ps and measurement range of 3.4 ns are achieved based on a two-stage time interpolatio…
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Design Methodologies for Low-Jitter CMOS Clock Distribution Open
Clock jitter negatively affects the performance of sampling circuits such as high-speed wireline transceivers and data converters. With CMOS buffers being increasingly used for the distribution of precise clocks in advanced technologies, i…
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A generation and distribution system of clock signal source for signal acquisition system Open
The clock signal is the heartbeat of modern electronic system, and demands of increasing high‐quality signal has been raised, with the development of science and technology in the field of electronic information. The clock signal with low …
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Measures to Improve the Accuracy and Reliability of Clock Synchronization in Time-Sensitive Networking Open
Most of the time-sensitive networking standards are based on a high precise and reliability time reference, which is accomplished by IEEE 802.1 AS. However, the accuracy and reliability of clock synchronization could be affected in practic…
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A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems Open
An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digital multiplying delay-locked lo…
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Pair Nodes Clock Synchronization Algorithm Based on Kalman Filter for Underwater Wireless Sensor Networks Open
Time synchronization is the basis of many applications. Aiming at the limitations of the existing clock synchronization algorithms in underwater wireless sensor networks, we propose a pairwise synchronization algorithm called K-Sync, which…
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Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit Open
Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling …
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Improved Clock Synchronization Algorithms for the Controller Area Network (CAN) Open
Safety-critical in-vehicle applications require an accurate global time in order to coordinate their actions. Although Controller Area Network (CAN) is the most widely used in-vehicle communication bus, it does not support synchronized clo…
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Development Board Implementation and Chip Design of IEEE 1588 Clock Synchronization System Applied to Computer Networking Open
With the vigorous development of industrial automation and the Internet of things, the transmission of data is more dependent on immediacy, so network devices have higher and higher requirements for time synchronization accuracy. The clock…
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Microcontroller-Based Kurdish Understandable and Readable Digital Smart Clock Open
A smart clock is any digital clock that has at least one intelligent feature. Moreover, it provides time with synchronizing automatically base on the standard measurement, which is determined during the implementation software on the hardw…
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An Enhanced Method for Nanosecond Time Synchronization in IEEE 1588 Precision Time Protocol Open
The performance of time-critical systems depends heavily on time synchronization accuracy. Therefore, it is crucial to have a synchronization method that can achieve high time synchronization accuracy. In this paper, we propose a new under…
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A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers Open
This paper presents an efficient solution to reduce the power consumption of the popular linear feedback shift register by exploiting the gated clock approach. The power reduction with respect to other gated clock schemes is obtained by an…
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Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators Open
With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable ch…
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HEX: Scaling honeycombs is easier than scaling clock trees Open
We argue that a hexagonal grid with simple intermediate nodes is a robust alternative to buffered clock trees typically used for clock distribution in VLSI circuits, multi-core processors, and other applications that require accurate synch…
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Research and Implementation of Clock Synchronization Technology Based on PTP Open
With the rapid development of power system, the requirement of network clock synchronization accuracy is becoming higher and higher, in many cases, it needs to reach microsecond level. In order to meet the increasing demand, based on the a…