Sample and hold ≈ Sample and hold
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FlexED8: the first member of a fast and flexible sample-changer family for macromolecular crystallography Open
Automated sample changers are now standard equipment for modern macromolecular crystallography synchrotron beamlines. Nevertheless, most are only compatible with a single type of sample holder and puck. Recent work aimed at reducing sample…
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An Introduction to High Sample Rate Nyquist Analog-to-Digital Converters Open
Increasingly wider band analog signals found in multiple information and communication technology applications, requiring real-time digital signal processing, demand analog-to-digital converters with ever higher sample rate. Several innova…
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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications Open
This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development…
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Analog Circuit Generator based on Deep Neural Network enhanced Combinatorial Optimization Open
A deep neural network (DNN) based stochastic combinatorial optimization framework is presented that can find the optimal sizing of circuits in a sample-efficient manner. This sample efficiency allows us to unify this framework with generat…
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A fast TIADC calibration method for 5GSPS digital storage oscilloscope Open
Time-interleaved analog to digital convertor (TIADC) is widely used in engineering to increase the sample rate of acquisition system. However, the mismatches between sub-ADCs in TIADC system result in the distortion of sample output and de…
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8-Bit 250-MS/s ADC Based on SAR Architecture with Novel Comparator at 70 nm Technology Node Open
The data converters are prerequisite for digital processing of analog signals. SAR ADC is preferred for their good balance between speed, area and power considerations. In this paper, we proposed a novel comparator design based on double t…
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Bootstrapped switch with improved linearity based on a negative-voltage bootstrapped capacitor Open
This study introduces a new bootstrapped switch for improving sampling linearity. In this technology, the introduction of a negative-voltage bootstrap capacitor reduces the parasitic capacitance at the critical signal node, thus improving …
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Development of a Front-End ASIC for 1D Detectors with 12 MHz Frame-Rate Open
We present a front-end readout ASIC developed for a new family of ultra-fast 1D imaging detectors operating at frame rates of up to 12 MHz. The ASIC, realized in 110 nm CMOS technology, is designed to be compatible with different semicondu…
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Design and Simulation of 4-Bit Flash Analog to Digital Converter (ADC) for High Speed Applications Open
Objective: To design 4-bit flash Analog to Digital Converter (ADC) for high speed applications. The objectives of the project are to design sample and hold circuit, high efficient DAC circuit, to design a high speed, low power and minimum …
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Power Efficient Simple Technique to Convert a Reset-and-Hold Into a True-Sample-and-Hold Using an Auxiliary Output Stage Open
A technique to implement true-sample-and-hold circuits that hold the output for almost the entire clock cycle without resetting to zero is introduced, alleviating the slew rate requirement on the op-amp. It is based on a Miller op-amp with…
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Design of a High Speed and Low Power Sample and Hold Circuit for 16 Bit ADC Open
Data plays an important role in the present world where the communications are becoming so crucial. Data acquisition and communication systems are in need ofhigherresolution (i.e., 16 Bits)ADCs. The successive approximation (SAR) ADCis sui…
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Using Probabilistic Model Rollouts to Boost the Sample Efficiency of Reinforcement Learning for Automated Analog Circuit Sizing Open
sponsorship: European Research Council|101019982
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High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit Open
A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap …
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RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL Open
Analog/mixed-signal circuit design is one of the most complex and time-consuming stages in the whole chip design process. Due to various process, voltage, and temperature (PVT) variations from chip manufacturing, analog circuits inevitably…
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Design an Improved Structure for 10-Bit Pipeline Analog to Digital Converter Based on 0.18µm CMOS Technology Open
This paper proposed a novel structure of a 10-bit, 400MS/s pipelined analog to digital convertor using 0.18 µm TSMC technology. In this paper, two stages are used to converter design and a new method is proposed to increase the speed of th…
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Stability of Zeros for Sampled-Data Models with Triangle Sample and Hold Implemented by Zero-Order Hold Open
This paper deals with the stability characteristics of zeros for sampled-data models with a class of triangle sample and hold realized by a traditional zero-order hold. For any controlled models in the modern industrial system, using a dig…
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The Design of a Low-Power Pipelined ADC for IoT Applications Open
This paper proposes a low-power 10-bit 20 MS/s pipelined analog-to-digital converter (ADC) designed for the burgeoning needs of low-data-rate communication systems, particularly within the Internet of Things (IoT) domain. To reduce power u…
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Enabling Fine Sample Rate Settings in DSOs with Time-Interleaved ADCs Open
The time-base used by digital storage oscilloscopes allows limited selections of the sample rate, namely constrained to a few integer submultiples of the maximum sample rate. This limitation offers the advantage of simplifying the data tra…
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A 0.9-Nyquist-Band Digital Timing Mismatch Correction for Time-Interleaved ADCs Achieving Delay Tuning Range of 0.12-Sample-Period Open
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Design and implementation of an analog signal isolation conditioning circuit Open
In control systems, external analog signals need to be converted into digital signals. When sampling external input analog signals, such as voltage or current, it is necessary to process the small analog signal amplification or large signa…
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A Sample-and- Hold Circuit for a Resolution Pipelined ADC Open
A sample-and- hold circuit for a resolution pipelined ADC is presented. The circuit uses a fully differential capacitor flip structure to reduce power consumption. Increase the gain by using an olded-cascode amplifier. Based on 0.35μm CMOS…
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Performance Assessment of Several Low-Cost Consumer-Grade Analog-to-Digital Conversion Devices Open
The Oak Ridge National Laboratory (ORNL) has pioneered an approach where low-cost consumer-grade electronics can be used as the basis of a highly reliable data acquisition architecture. One twenty-channel system based on this approach has …
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Comparison of Low Power High Speed Comparator for Flash ADC Open
The analog to digital converter (ADC), a bridge between digital world and analog world, plays a crucial role in the modern semiconductor industry. Among different types of ADCs, the flash ADC (also known as the direct-conversion ADC) is ex…
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A full sample-type magneto-impedance (MI) magnetometer with programmable circuit for high compatibility Open
In this study, a programmable Magneto-Impedance (MI) sensor circuit has been designed by using a Field-Programmable-Gate-Arrays (FPGA), and an operational amplifier integrator has been used to replace the peak hold circuit in the conventio…
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ANALYSIS AND DESIGN OF A NEW STRUCTURE FOR 10-BIT 350MS/S PIPELINE ANALOG TO DIGITAL CONVERTER Open
A 10-bit pipelined Analog to Digital converter is proposed in this paper with using 0.18 µm TSMC technology. In this paper, a new structure is proposed to increase the speed of the pipeline analog to digital convertor. So at the first stag…
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eSampling: Energy Harvesting ADCs Open
Analog-to-digital converters (ADCs) allow physical signals to be processed using digital hardware. The power consumed in conversion grows with the sampling rate and quantization resolution, imposing a major challenge in power-limited syste…
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Sampling circuit issues in A/D converters and challenges for the solution Open
This paper discusses issues of sampling circuits in analog-to-digital converter (ADC) and reviews some papers describing challenges for the solution to this fundamental issue of ADC. The energy consumption of the ADC is essentially determi…
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Fully Digital Second-order Level-crossing Sampling ADC for Data Saving in Sensing Sparse Signals Open
This paper presents a fully integrated second-order level-crossing sampling data converter for real-time data compression and feature extraction. Compared with level-sampling ADCs which sample at fixed voltage levels, the proposed circuits…
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Preliminary result on stochastic system control theory for aperiod sample-data systems Open
In this paper, we obtain some preliminary results on stochastic control theory for time-varying linear systems both continuous and discrete, and further apply to aperiod sample-data linear systems. The Ito's lemma is utilized in this propo…
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A 2 GSps, 8-Bit Folding and Interpolation ADC with Foreground Calibration in 90 nm CMOS Technology Open
A single channel 2 GSps, 8-bit folding and interpolation (F&I) analog-to-digital converter (ADC) with foreground calibration in TSMC 90 nm CMOS technology is presented in this paper. The ADC utilizes cascaded folding, which incorporates an…