Flat memory model
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DRISA Open
Data movement between the processing units and the memory in traditional von Neumann architecture is creating the "memory wall" problem. To bridge the gap, two approaches, the memory-rich processor (more on-chip memory) and the compute-cap…
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Memory materials and devices: From concept to application Open
Memory cells have always been an important element of information technology. With emerging technologies like big data and cloud computing, the scale and complexity of data storage has reached an unprecedented peak with a much higher requi…
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Device and Circuit Architectures for In‐Memory Computing Open
With the rise in artificial intelligence (AI), computing systems are facing new challenges related to the large amount of data and the increasing burden of communication between the memory and the processing unit. In‐memory computing (IMC)…
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Can far memory improve job throughput? Open
As memory requirements grow, and advances in memory technology slow, the availability of sufficient main memory is increasingly the bottleneck in large compute clusters. One solution to this is memory disaggregation, where jobs can remotel…
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SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput Open
In-memory processing can dramatically improve the latency and energy consumption of computing systems by minimizing the data transfer between the memory and the processor. Efficient execution of processing operations within the memory is t…
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Clio: a hardware-software co-designed disaggregated memory system Open
Memory disaggregation has attracted great attention recently because of its benefits in efficient memory utilization and ease of management. So far, memory disaggregation research has all taken one of two approaches: building/emulating mem…
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Optically Disaggregated Data Centers With Minimal Remote Memory Latency: Technologies, Architectures, and Resource Allocation [Invited] Open
Disaggregated rack-scale data centers have been proposed as the only promising avenue to break the barrier of the fixed CPU-to-memory proportionality caused by main-tray direct-attached conventional/traditional server-centric systems. Howe…
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A Framework for Memory Oversubscription Management in Graphics Processing Units Open
Modern discrete GPUs support unified memory and demand paging. Automatic management of data movement between CPU memory and GPU memory dramatically reduces developer effort. However, when application working sets exceed physical memory cap…
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Performance characterization of a DRAM-NVM hybrid memory architecture for HPC applications using intel optane DC persistent memory modules Open
Non-volatile, byte-addressable memory (NVM) has been introduced by Intel in the form of NVDIMMs named Intel® Optane™ DC PMM. This memory module has the ability to persist the data stored in it without the need for power. This expands the m…
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IMAGING: In-Memory AlGorithms for Image processiNG Open
Data-intensive applications such as image processing suffer from massive data movement between memory and processing units. The severe limitations on system performance and energy efficiency imposed by this data movement are further exacer…
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New Logic-In-Memory Paradigms: An Architectural and Technological Perspective Open
Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as M…
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Static Memory Deduplication for Performance Optimization in Cloud Computing Open
In a cloud computing environment, the number of virtual machines (VMs) on a single physical server and the number of applications running on each VM are continuously growing. This has led to an enormous increase in the demand of memory cap…
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Umpire: Application-focused management and coordination of complex hierarchical memory Open
Advanced architectures like Sierra provide a wide range of memory resources that must often be carefully controlled by the user. These resources have varying capacities, access timing rules, and visibility to different compute resources. A…
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A New Approach to Automatic Memory Banking using Trace-Based Address Mining Open
Recent years have seen an increased deployment of FPGAs as programmable accelerators for improving the performance and energy efficiency of compute-intensive applications. A well-known "secret sauce" of achieving highly efficient FPGA acce…
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RACER: Bit-Pipelined Processing Using Resistive Memory Open
To combat the high energy costs of moving data between main memory and the CPU, recent works have proposed to perform processing-using-memory (PUM), a type of processing-in-memory where operations are performed on data in situ (i.e., right…
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On the Memory Underutilization: Exploring Disaggregated Memory on HPC Systems Open
Large-scale high-performance computing (HPC) systems consist of massive compute and memory resources tightly coupled in nodes. We perform a large-scale study of memory utilization on four production HPC clusters. Our results show that more…
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Contention-Aware Dynamic Memory Bandwidth Isolation with Predictability in COTS Multicores: An Avionics Case Study Open
Airbus is investigating COTS multicore platforms for safety-critical avionics applications, pursuing helicopter-style autonomous and electric aircraft. These aircraft need to be ultra-lightweight for future mobility in the urban city lands…
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Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture Open
Modern computing applications require more and more data to be processed. Unfortunately, the trend in memory technologies does not scale as fast as the computing performances, leading to the so called memory wall. New architectures are cur…
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Disaggregated Cloud Memory with Elastic Block Management Open
With the growing importance of in-memory data processing, cloud service providers have launched large memory virtual machine services to accommodate memory intensive workloads. Such large memory services using low volume scaled-up machines…
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Near-Memory Address Translation Open
Virtual memory (VM) is a crucial abstraction in modern computer systems at any scale, from handheld devices to datacenters. VM provides programmers the illusion of an always sufficiently large and linear memory, making programming easier. …
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NumaMMA Open
International audience
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MTM: Rethinking Memory Profiling and Migration for Multi-Tiered Large Memory Open
Multi-terabyte large memory systems are often characterized by more than two memory tiers with different latency and bandwidth. Multi-tiered large memory systems call for rethinking of memory profiling and migration because of the unique p…
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Simple DRAM and Virtual Memory Abstractions to Enable Highly Efficient Memory Systems Open
In most modern systems, the memory subsystem is managed and accessed at multiple different granularities at various resources. We observe that such multi-granularity management results in significant inefficiency in the memory subsystem. S…
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FlexNN: Efficient and Adaptive DNN Inference on Memory-Constrained Edge Devices Open
Due to the popularity of deep neural networks (DNNs) and considerations over network overhead, data privacy, and inference latency, there is a growing interest in deploying DNNs to edge devices in recent years. However, the limited memory …
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An Energy-Efficient and Fast Scheme for Hybrid Storage Class Memory in an AIoT Terminal System Open
Conventional main memory can no longer meet the requirements of low energy consumption and massive data storage in an artificial intelligence Internet of Things (AIoT) system. Moreover, the efficiency is decreased due to the swapping of da…
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MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memory Open
In recent years, we are witnessing a trend toward in-memory computing for future generations of computers that differs from traditional von-Neumann architecture in which there is a clear distinction between computing and memory units. Cons…
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Skyrmion Logic-In-Memory Architecture for Maximum/Minimum Search Open
In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with the performance gap between memory and logic, impacts heavily on algorithms performance,…
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A memory scheduling strategy for eliminating memory access interference in heterogeneous system Open
Multiple CPUs and GPUs are integrated on the same chip to share memory, and access requests between cores are interfering with each other. Memory requests from the GPU seriously interfere with the CPU memory access performance. Requests be…
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Mira: A Program-Behavior-Guided Far Memory System Open
Far memory, where memory accesses are non-local, has become more popular in recent years as a solution to expand memory size and avoid memory stranding. Prior far memory systems have taken two approaches: transparently swap memory pages be…
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TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory Open
The increasing demand for memory in hyperscale applications has led to memory becoming a large portion of the overall datacenter spend. The emergence of coherent interfaces like CXL enables main memory expansion and offers an efficient sol…