Software pipelining
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TANGRAM Open
The use of increasingly larger and more complex neural networks (NNs) makes it critical to scale the capabilities and efficiency of NN accelerators. Tiled architectures provide an intuitive scaling solution that supports both coarse-graine…
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Fault-tolerance and two-level pipelining in VLSI systolic arrays Open
Computer Science Department
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Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis Open
Current pipelining approach in high-level synthesis (HLS) achieves high performance for applications with regular and statically analyzable memory access patterns. However, it cannot effectively handle infrequent data-dependent structural …
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From functional programs to pipelined dataflow circuits Open
We present a translation from programs expressed in a functional IR into dataflow networks as an intermediate step within a Haskell-to-Hardware compiler. Our networks exploit pipeline parallelism, particularly across multiple tail-recursiv…
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Design of Very High-Speed Pipeline FIR Filter Through Precise Critical Path Analysis Open
In this paper, we propose a new hardware architecture of a very high-speed finite impulse response (FIR) filter using fine-grained seamless pipelining. The proposed full-parallel pipeline FIR filter can produce an output sample in a few ga…
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Toward Speculative Loop Pipelining for High-Level Synthesis Open
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RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining Open
RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV…
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High throughput and energy efficient FIR filter architectures using retiming and two level pipelining Open
A methodology to improve the throughput and energy efficiency of finite impulse response (FIR) filters through the effective application of retiming and two-level pipelining is presented in this paper. Improving throughput and energy effic…
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High-Speed DSP Pipelining and Retiming techniques for Distributed-Arithmetic RNS-based FIR Filter Design Open
Digital FIR Filters plays a major role in many signal processing applications. Generally, these filters are designed with multipliers and adders to find the filter output. This paper acquaints how to reduce the complexity of higher order F…
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Design and Implementation of a Five Stage Pipelining Architecture Simulator for RiSC-16 Instruction Set Open
In modern computing, multitasking is the most favorable aspect. An un-pipelined instruction cycle (fetch-execute cycle) CPU processes instructions one after another increasing duration at lesser speed in completing tasks. With pipelined co…
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Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning Open
Loop pipelining is an important optimization in high-level synthesis to enable high-throughput pipelined execution of loop iterations. However, current pipeline scheduling approach relies on fundamentally inexact heuristics based on ad hoc…
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Directive-Based Pipelining Extension for OpenMP Open
Programming models like CUDA, OpenMP, OpenACC and OpenCL are designed to offload compute-intensive workloads to accelerators efficiently. However, the naive offload model, which synchronously copies and executes in sequence, requires exten…
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High-Throughput Message Digest (MD5) Design and Simulation-Based Power Estimation Using Unfolding Transformation Open
The high throughput of the cryptographic hash function has become an important aspect of the hardware implementation of security system design. There are several methods that can be used to improve the throughput performance of MD5 design.…
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Automatic Pipelining and Vectorization of Scientific Code for FPGAs Open
There is a large body of legacy scientific code in use today that could benefit from execution on accelerator devices like GPUs and FPGAs. Manual translation of such legacy code into device-specific parallel code requires significant manua…
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Design and Implementation of Third Order Low Pass Digital FIR Filter using Pipelining Retiming Technique Open
This paper presents design and implementation of 3rd order low pass digital FIR filter using pipelining retiming technique. Aim of this paper is to apply pipelining retiming technique on low pass digital FIR filter and compare with the exi…
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Optimising Multiprocessor Image-Based Control Through Pipelining and Parallelism Open
Image-based control (IBC) systems have a long sensing delay due to compute-intensive image processing. Modern multiprocessor IBC implementations consider either parallelisation of the sensing task or pipelining of the control loop to cope …
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Improving Energy Efficiency of Coarse-Grain Reconfigurable Arrays Through Modulo Schedule Compression/Decompression Open
Modulo-scheduled course-grain reconfigurable array (CGRA) processors excel at exploiting loop-level parallelism at a high performance per watt ratio. The frequent reconfiguration of the array, however, causes between 25% and 45% of the con…
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DESIGN OF RISC PROCESSOR USING VHDL Open
The aim of the paper is to design a 16-bit RISC processor. It is having five stage pipelining which is designed using VHDL. RISC processors have a unique feature called pipelining. Pipelining is used to make processor faster. In Pipelining…
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Software Pipelining for Quantum Loop Programs Open
We propose a method for performing software pipelining on quantum for-loop programs, exploiting parallelism in and across iterations. We redefine concepts that are useful in program optimization, including array aliasing, instruction depen…
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Improving Pipelining Tools for Pre-processing Data. Open
The last several years have seen the emergence of data mining and its transformation into a powerful tool that adds value to business and research. Data mining makes it possible to explore and find unseen connections between variables and …
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VLSI design for efficient RSD-Based ECC processor using Karatsuba algorithm Open
In this paper, an exportable application-particular direction set elliptic bend cryptography processor in view of repetitive marked digit portrayal is proposed. The processor utilizes broad pipelining strategies for Karatsuba– Of man strat…
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ALCOP: Automatic Load-Compute Pipelining in Deep Learning Compiler for AI-GPUs Open
Pipelining between data loading and computation is a critical tensor program optimization for GPUs. In order to unleash the high performance of latest GPUs, we must perform a synergetic optimization of multi-stage pipelining across the mul…
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Similarity-Aware Architecture/Compiler Co-Designed Context-Reduction Framework for Modulo-Scheduled CGRA Open
Modulo-scheduled coarse-grained reconfigurable array (CGRA) processors have shown their potential for exploiting loop-level parallelism at high energy efficiency. However, these CGRAs need frequent reconfiguration during their execution, w…
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Energy-aware task scheduling for streaming applications on NoC-based MPSoCs Open
Streaming applications are being extensively run on portable embedded systems, which are battery-operated and with limited memory. Thus, minimizing the total energy consumption of such a system is important. We investigate the problem of o…
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A Performance Prediction-based DNN Partitioner for Edge TPU Pipelining Open
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Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis Open
High-level synthesis has been widely recognized and accepted as an efficient compilation process targeting field-programmable gate arrays for algorithm evaluation and product prototyping. However, the massively parallel memory access deman…
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Introducing software pipelining for the A64FX processor into LLVM Open
Software pipelining is an essential optimization for accelerating High-Performance Computing(HPC) applications on CPUs. Modern CPUs achieve high performance through many-core and wide SIMD instructions. Software pipelining is an optimizati…
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Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays Open
While coarse-grained reconfigurable arrays (CGRAs) have emerged as promising programmable accelerator architectures, pipelining applications running on CGRAs is required to ensure high maximum clock frequencies. Current CGRA compilers eith…
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Experimenting with Hybrid Quantum Optimization in HPC Software Stack for CPU Register Allocation Open
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Offset Pipelining for Coarse Grain Reconfigurable Arrays Open
This dissertation presents an execution model and compilation algorithms to advance the utility of coarse-grained reconfigurable arrays (CGRAs). These time multiplexed, spatial architectures can provide improved energy efficiency and perfo…