Single event upset
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Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance Open
The history of integrated circuit (IC) development is another record of human challenges involving space. Efforts have been made to protect ICs from sudden malfunctions due to single-event effects (SEEs). These effects are triggered by onl…
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Soft-Error-Immune Read-Stability-Improved SRAM for Multi-Node Upset Tolerance in Space Applications Open
With aggressive scaling of transistor size and supply voltage, the critical charge of the sensitive nodes is reducing rapidly. As a result, when these deep submicron devices are used in memory cells in the space environment, single-event u…
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Heavy Ion and Proton-Induced Single Event Upset Characteristics of a 3-D NAND Flash Memory Open
We evaluated the effects of heavy ion and proton irradiation for a 3D NAND flash. The 3D NAND showed similar single-event upset (SEU) sensitivity to a planar NAND of identical density in the multiple-cell level (MLC) storage mode. The 3D N…
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Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments Open
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A novel self-recoverable and triple nodes upset resilience DICE latch Open
With the CMOS technology scaling down, the normal latch is more susceptible to soft errors caused by radiation particles. In this paper, we proposed a low-power and highly reliable radiation hardened latch to enhance the single event upset…
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A Hybrid Fault-Tolerant LEON3 Soft Core Processor Implemented in Low-End SRAM FPGA Open
In this work we implemented a hybrid fault-tolerant LEON3 soft-core processor in a low-end FPGA (Artix-7) and evaluated its error detection capabilities through neutron irradiation and fault injection in an incremental manner. The error mi…
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ACME: A Tool to Improve Configuration Memory Fault Injection in SRAM-Based FPGAs Open
Circuits in harsh environments, as space, tend to suffer severe problems caused by radiation. In this scenario, where the behavior of the system can be jeopardized, it is critical to produce fault tolerant circuits that can operate correct…
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Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets Open
This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs). First, the QCCM10T cell consisting of four cross-coupl…
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Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low Power and Low-Orbit Aerospace Applications Open
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Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode Open
A sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identifie…
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Physical Mechanisms Inducing Electron Single-Event Upset Open
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Heavy Ion Energy Deposition and SEE Intercomparison Within the RADNEXT Irradiation Facility Network Open
RADNEXT is an EU-funded network of irradiation facilities and radiation effects’ experts aimed at increasing the quantity and quality of user access to accelerator infrastructure and improving the diversity and harmonization across facilit…
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Simplified SEE Sensitivity Screening for COTS Components in Space Open
We introduce an approach aimed at prescreening COTS components according to their single-event effect (SEE) sensitivity for space missions in which a complete characterization of their individual response to protons and heavy ions is not f…
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Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications Open
With technology scaling, transistor sizing, as well as the distance between them, is decreasing rapidly, thereby reducing the critical charge of sensitive nodes. This reduction makes SRAM cells, used for aerospace applications, more suscep…
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Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA Open
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Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology Open
In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs). Moreover, they show a hi…
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Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip Open
A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of stand…
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Physical Mechanisms of Proton-Induced Single-Event Upset in Integrated Memory Devices Open
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Thermal Neutron-Induced SEUs in the LHC Accelerator Environment Open
In addition to high-energy hadrons, which include neutrons, protons, and pions above 20 MeV, thermal neutrons (ThNs) are a major concern in terms of soft error rate (SER) for electronics operating in the large hadron collider (LHC) acceler…
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Solar Particle Event and Single Event Upset Prediction from SRAM-based Monitor and Supervised Machine Learning Open
The intensity of cosmic radiation may differ over five orders of magnitude within a few hours or days during the Solar Particle Events (SPEs), thus increasing for several orders of magnitude the probability of Single Event Upsets (SEUs) in…
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Investigation of Radiation Hardened TFET SRAM Cell for Mitigation of Single Event Upset Open
This study analyzes the soft error sensitivity of SRAM cell which employs double-gate tunnel field effect transistor (DG TFET). The mitigation technique for the data recovery after the heavy ion strike is discussed. The conventional 6T TFE…
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Single-Event Characterization of 16 nm FinFET Xilinx UltraScale+ Devices with Heavy Ion and Neutron Irradiation Open
This study examines the single-event response of Xilinx 16nm FinFET UltraScale+ FPGA and MPSoC device families. Heavy-ion single-event latch-up, single-event upsets in configuration SRAM, BlockRAM™ memories, and flip-flops, and neutron-ind…
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Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets in a NAND Flash Memory Open
We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found the single-event upset (SEU) cross section varied inversely with fluence. The SEU cross section decreased with increasing fluence. We at…
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On-Orbit Upset Rate Prediction at Advanced Technology Nodes: a 28 nm FD-SOI Case Study Open
We address accurate computation of on-orbit upset rates in advanced technologies, with a focus on FD-SOI at the 28 nm node. Heavy-ion measurements performed on FD-SOI SRAM bit-cells give experimental evidence of the technology's intrinsic …
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Single-Event Upset Cross-Section Trends for D-FFs at the 5- and 7-nm Bulk FinFET Technology Nodes Open
At each advanced technology node, it is crucial to characterize and understand the mechanisms affecting performance and reliability. Scaling for all nodes prior to the 5-nm bulk FinFET node had resulted in a decrease in single-event upset …
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SEU Characterization of Three Successive Generations of COTS SRAMs at Ultralow Bias Voltage to 14.2-MeV Neutrons Open
This paper presents a SEU sensitivity characterization at ultra-low bias voltage of three generations of COTS SRAMs manufactured in 130 nm, 90 nm and 65 nm CMOS processes. For this purpose, radiation tests with 14.2 MeV neutrons were perfo…
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An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays Open
As the microelectronics technology continuously advances to deep submicron scales, the occurrence of Multiple Cell Upset (MCU) induced by radiation in memory devices becomes more likely to happen. The implementation of a robust Error Corre…
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Heavy-Ion Induced Single Event Upsets in Advanced 65 nm Radiation Hardened FPGAs Open
The 65 nm Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) was designed and manufactured, which employed tradeoff radiation hardening techniques in Configuration RAMs (CRAMs), Embedded RAMs (EBRAMs) and flip-fl…
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A novel highly reliable and low-power radiation hardened SRAM bit-cell design Open
In this paper, an improved SEU hardened SRAM bit-cell, based on the SEU physics mechanism and reasonable circuit-design, is proposed. The proposed SRAM cell can offer differential read operation for robust sensing. By using 90 nm standard …
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Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions Open
Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects. However, the import…