EMS Article Swipe

PDF

Related Concepts

dataflow computer science exploit computer architecture reuse parallel computing interconnection parallelism (grammar) architecture embedded system engineering computer network visual arts waste management computer security art

Liancheng Jia , Yuyue Wang , Jingwen Leng , Yun Liang ·

YOU? · · 2022 · Open Access · · DOI: https://doi.org/10.1145/3489517.3530411 · OA: W4293023583

Spatial accelerators provide massive parallelism with an array of homogeneous PEs, and enable efficient data reuse with PE array dataflow and on-chip memory. Many previous works have studied the dataflow architecture of spatial accelerators, including performance analysis and automatic generation. However, existing accelerator generators fail to exploit the entire memory-level reuse opportunities, and generate suboptimal designs with data duplication and inefficient interconnection.